9. Machine Dependent Features

The machine instruction sets are (almost by definition) different on each machine where as runs. Floating point representations vary as well, and as often supports a few additional directives or command-line options for compatibility with other assemblers on a particular platform. Finally, some versions of as support special pseudo-instructions for branch optimization.

This chapter discusses most of these differences, though it does not include details on any machine's instruction set. For details on that subject, see the hardware manufacturer's manual.

9.1 Alpha Dependent Features
9.2 ARC Dependent Features
9.3 ARM Dependent Features
9.4 AVR Dependent Features
9.5 Blackfin Dependent Features
9.6 CR16 Dependent Features
9.7 CRIS Dependent Features
9.8 D10V Dependent Features
9.9 D30V Dependent Features
9.10 H8/300 Dependent Features		Renesas H8/300 Dependent Features
9.11 HPPA Dependent Features
9.12 ESA/390 Dependent Features		IBM ESA/390 Dependent Features
9.13 80386 Dependent Features		Intel 80386 and AMD x86-64 Dependent Features
9.14 Intel i860 Dependent Features		Intel 80860 Dependent Features
9.15 Intel 80960 Dependent Features
9.16 IA-64 Dependent Features		Intel IA-64 Dependent Features
9.17 IP2K Dependent Features
9.18 LM32 Dependent Features
9.19 M32C Dependent Features
9.20 M32R Dependent Features
9.21 M680x0 Dependent Features
9.22 M68HC11 and M68HC12 Dependent Features		M68HC11 and 68HC12 Dependent Features
9.23 MicroBlaze Dependent Features		MICROBLAZE Dependent Features
9.24 MIPS Dependent Features
9.25 MMIX Dependent Features
9.26 MSP 430 Dependent Features
9.32 Renesas / SuperH SH Dependent Features
9.33 SuperH SH64 Dependent Features
9.27 PDP-11 Dependent Features
9.28 picoJava Dependent Features
9.29 PowerPC Dependent Features
9.30 IBM S/390 Dependent Features
9.31 SCORE Dependent Features
9.34 SPARC Dependent Features
9.35 TIC54X Dependent Features		TI TMS320C54x Dependent Features
9.39 v850 Dependent Features		V850 Dependent Features
9.40 Xtensa Dependent Features
9.36 Z80 Dependent Features
9.37 Z8000 Dependent Features
9.38 VAX Dependent Features

9.1 Alpha Dependent Features

9.1.1 Notes
9.1.2 Options
9.1.3 Syntax
9.1.4 Floating Point
9.1.5 Alpha Assembler Directives		Alpha Machine Directives
9.1.6 Opcodes

9.1.1 Notes

The documentation here is primarily for the ELF object format. as also supports the ECOFF and EVAX formats, but features specific to these formats are not yet documented.

9.1.2 Options

`-mcpu'

This option specifies the target processor. If an attempt is made to assemble an instruction which will not execute on the target processor, the assembler may either expand the instruction as a macro or issue an error message. This option is equivalent to the .arch directive.

The following processor names are recognized: 21064, 21064a, 21066, 21068, 21164, 21164a, 21164pc, 21264, 21264a, 21264b, ev4, ev5, lca45, ev5, ev56, pca56, ev6, ev67, ev68. The special name all may be used to allow the assembler to accept instructions valid for any Alpha processor.

In order to support existing practice in OSF/1 with respect to .arch, and existing practice within MILO (the Linux ARC bootloader), the numbered processor names (e.g. 21064) enable the processor-specific PALcode instructions, while the "electro-vlasic" names (e.g. ev4) do not.

`-mdebug'

`-no-mdebug'

Enables or disables the generation of .mdebug encapsulation for stabs directives and procedure descriptors. The default is to automatically enable .mdebug when the first stabs directive is seen.

`-relax'

This option forces all relocations to be put into the object file, instead of saving space and resolving some relocations at assembly time. Note that this option does not propagate all symbol arithmetic into the object file, because not all symbol arithmetic can be represented. However, the option can still be useful in specific applications.

`-replace'

`-noreplace'

Enables or disables the optimization of procedure calls, both at assemblage and at link time. These options are only available for VMS targets and -replace is the default. See section 1.4.1 of the OpenVMS Linker Utility Manual.

`-g'

This option is used when the compiler generates debug information. When gcc is using mips-tfile to generate debug information for ECOFF, local labels must be passed through to the object file. Otherwise this option has no effect.

`-Gsize'

A local common symbol larger than size is placed in .bss, while smaller symbols are placed in .sbss.

`-F'

`-32addr'

These options are ignored for backward compatibility.

9.1.3 Syntax

9.1.3.1 Special Characters
9.1.3.2 Register Names
9.1.3.3 Relocations

9.1.3.1 Special Characters

`#' is the line comment character.

`;' can be used instead of a newline to separate statements.

9.1.3.2 Register Names

The 32 integer registers are referred to as `$n' or `$rn'. In addition, registers 15, 28, 29, and 30 may be referred to by the symbols `$fp', `$at', `$gp', and `$sp' respectively.

The 32 floating-point registers are referred to as `$fn'.

9.1.3.3 Relocations

Some of these relocations are available for ECOFF, but mostly only for ELF. They are modeled after the relocation format introduced in Digital Unix 4.0, but there are additions.

The format is `!tag' or `!tag!number' where tag is the name of the relocation. In some cases number is used to relate specific instructions.

The relocation is placed at the end of the instruction like so:

ldah $0,a($29) !gprelhigh lda $0,a($0) !gprellow ldq $1,b($29) !literal!100 ldl $2,0($1) !lituse_base!100

!literal

!literal!N

Used with an ldq instruction to load the address of a symbol from the GOT.

A sequence number N is optional, and if present is used to pair lituse relocations with this literal relocation. The lituse relocations are used by the linker to optimize the code based on the final location of the symbol.

Note that these optimizations are dependent on the data flow of the program. Therefore, if any lituse is paired with a literal relocation, then all uses of the register set by the literal instruction must also be marked with lituse relocations. This is because the original literal instruction may be deleted or transformed into another instruction.

Also note that there may be a one-to-many relationship between literal and lituse, but not a many-to-one. That is, if there are two code paths that load up the same address and feed the value to a single use, then the use may not use a lituse relocation.

!lituse_base!N

Used with any memory format instruction (e.g. ldl) to indicate that the literal is used for an address load. The offset field of the instruction must be zero. During relaxation, the code may be altered to use a gp-relative load.

!lituse_jsr!N

Used with a register branch format instruction (e.g. jsr) to indicate that the literal is used for a call. During relaxation, the code may be altered to use a direct branch (e.g. bsr).

!lituse_jsrdirect!N

Similar to lituse_jsr, but also that this call cannot be vectored through a PLT entry. This is useful for functions with special calling conventions which do not allow the normal call-clobbered registers to be clobbered.

!lituse_bytoff!N

Used with a byte mask instruction (e.g. extbl) to indicate that only the low 3 bits of the address are relevant. During relaxation, the code may be altered to use an immediate instead of a register shift.

!lituse_addr!N

Used with any other instruction to indicate that the original address is in fact used, and the original ldq instruction may not be altered or deleted. This is useful in conjunction with lituse_jsr to test whether a weak symbol is defined.

ldq $27,foo($29) !literal!1 beq $27,is_undef !lituse_addr!1 jsr $26,($27),foo !lituse_jsr!1

!lituse_tlsgd!N

Used with a register branch format instruction to indicate that the literal is the call to __tls_get_addr used to compute the address of the thread-local storage variable whose descriptor was loaded with !tlsgd!N.

!lituse_tlsldm!N

Used with a register branch format instruction to indicate that the literal is the call to __tls_get_addr used to compute the address of the base of the thread-local storage block for the current module. The descriptor for the module must have been loaded with !tlsldm!N.

!gpdisp!N

Used with ldah and lda to load the GP from the current address, a-la the ldgp macro. The source register for the ldah instruction must contain the address of the ldah instruction. There must be exactly one lda instruction paired with the ldah instruction, though it may appear anywhere in the instruction stream. The immediate operands must be zero.

bsr $26,foo ldah $29,0($26) !gpdisp!1 lda $29,0($29) !gpdisp!1

!gprelhigh

Used with an ldah instruction to add the high 16 bits of a 32-bit displacement from the GP.

!gprellow

Used with any memory format instruction to add the low 16 bits of a 32-bit displacement from the GP.

!gprel

Used with any memory format instruction to add a 16-bit displacement from the GP.

!samegp

Used with any branch format instruction to skip the GP load at the target address. The referenced symbol must have the same GP as the source object file, and it must be declared to either not use $27 or perform a standard GP load in the first two instructions via the .prologue directive.

!tlsgd

!tlsgd!N

Used with an lda instruction to load the address of a TLS descriptor for a symbol in the GOT.

The sequence number N is optional, and if present it used to pair the descriptor load with both the literal loading the address of the __tls_get_addr function and the lituse_tlsgd marking the call to that function.

For proper relaxation, both the tlsgd, literal and lituse relocations must be in the same extended basic block. That is, the relocation with the lowest address must be executed first at runtime.

!tlsldm

!tlsldm!N

Used with an lda instruction to load the address of a TLS descriptor for the current module in the GOT.

Similar in other respects to tlsgd.

!gotdtprel

Used with an ldq instruction to load the offset of the TLS symbol within its module's thread-local storage block. Also known as the dynamic thread pointer offset or dtp-relative offset.

!dtprelhi

!dtprello

!dtprel

Like gprel relocations except they compute dtp-relative offsets.

!gottprel

Used with an ldq instruction to load the offset of the TLS symbol from the thread pointer. Also known as the tp-relative offset.

!tprelhi

!tprello

!tprel

Like gprel relocations except they compute tp-relative offsets.

9.1.4 Floating Point

9.1.5 Alpha Assembler Directives

as for the Alpha supports many additional directives for compatibility with the native assembler. This section describes them only briefly.

These are the additional directives in as for the Alpha:

.arch cpu

Specifies the target processor. This is equivalent to the `-mcpu' command-line option. See section Options, for a list of values for cpu.

.ent function[, n]

Mark the beginning of function. An optional number may follow for compatibility with the OSF/1 assembler, but is ignored. When generating .mdebug information, this will create a procedure descriptor for the function. In ELF, it will mark the symbol as a function a-la the generic .type directive.

.end function

Mark the end of function. In ELF, it will set the size of the symbol a-la the generic .size directive.

.mask mask, offset

Indicate which of the integer registers are saved in the current function's stack frame. mask is interpreted a bit mask in which bit n set indicates that register n is saved. The registers are saved in a block located offset bytes from the canonical frame address (CFA) which is the value of the stack pointer on entry to the function. The registers are saved sequentially, except that the return address register (normally $26) is saved first.

This and the other directives that describe the stack frame are currently only used when generating .mdebug information. They may in the future be used to generate DWARF2 .debug_frame unwind information for hand written assembly.

.fmask mask, offset

Indicate which of the floating-point registers are saved in the current stack frame. The mask and offset parameters are interpreted as with .mask.

.frame framereg, frameoffset, retreg[, argoffset]

Describes the shape of the stack frame. The frame pointer in use is framereg; normally this is either $fp or $sp. The frame pointer is frameoffset bytes below the CFA. The return address is initially located in retreg until it is saved as indicated in .mask. For compatibility with OSF/1 an optional argoffset parameter is accepted and ignored. It is believed to indicate the offset from the CFA to the saved argument registers.

.prologue n

Indicate that the stack frame is set up and all registers have been spilled. The argument n indicates whether and how the function uses the incoming procedure vector (the address of the called function) in $27. 0 indicates that $27 is not used; 1 indicates that the first two instructions of the function use $27 to perform a load of the GP register; 2 indicates that $27 is used in some non-standard way and so the linker cannot elide the load of the procedure vector during relaxation.

.usepv function, which

Used to indicate the use of the $27 register, similar to .prologue, but without the other semantics of needing to be inside an open .ent/.end block.

The which argument should be either no, indicating that $27 is not used, or std, indicating that the first two instructions of the function perform a GP load.

One might use this directive instead of .prologue if you are also using dwarf2 CFI directives.

.gprel32 expression

Computes the difference between the address in expression and the GP for the current object file, and stores it in 4 bytes. In addition to being smaller than a full 8 byte address, this also does not require a dynamic relocation when used in a shared library.

.t_floating expression

Stores expression as an IEEE double precision value.

.s_floating expression

Stores expression as an IEEE single precision value.

.f_floating expression

Stores expression as a VAX F format value.

.g_floating expression

Stores expression as a VAX G format value.

.d_floating expression

Stores expression as a VAX D format value.

.set feature

Enables or disables various assembler features. Using the positive name of the feature enables while using `nofeature' disables.

at

Indicates that macro expansions may clobber the assembler temporary ($at or $28) register. Some macros may not be expanded without this and will generate an error message if noat is in effect. When at is in effect, a warning will be generated if $at is used by the programmer.

macro

Enables the expansion of macro instructions. Note that variants of real instructions, such as br label vs br $31,label are considered alternate forms and not macros.

move

reorder

volatile

These control whether and how the assembler may re-order instructions. Accepted for compatibility with the OSF/1 assembler, but as does not do instruction scheduling, so these features are ignored.

The following directives are recognized for compatibility with the OSF/1 assembler but are ignored.

.proc .aproc .reguse .livereg .option .aent .ugen .eflag .alias .noalias

9.1.6 Opcodes

9.2 ARC Dependent Features

9.2.1 Options
9.2.2 Syntax
9.2.3 Floating Point
9.2.4 ARC Machine Directives
9.2.5 Opcodes

9.2.1 Options

-marc[5|6|7|8]

This option selects the core processor variant. Using -marc is the same as -marc6, which is also the default.

arc5

Base instruction set.

arc6

Jump-and-link (jl) instruction. No requirement of an instruction between setting flags and conditional jump. For example:

mov.f r0,r1 beq foo

arc7

Break (brk) and sleep (sleep) instructions.

arc8

Software interrupt (swi) instruction.

Note: the .option directive can to be used to select a core variant from within assembly code.

-EB

This option specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor.

-EL

This option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor - this is the default.

9.2.2 Syntax

9.2.2.1 Special Characters
9.2.2.2 Register Names

9.2.2.1 Special Characters

*TODO*

9.2.2.2 Register Names

*TODO*

9.2.3 Floating Point

The ARC core does not currently have hardware floating point support. Software floating point support is provided by GCC and uses IEEE floating-point numbers.

9.2.4 ARC Machine Directives

The ARC version of as supports the following additional machine directives:

.2byte expressions

*TODO*

.3byte expressions

*TODO*

.4byte expressions

*TODO*

.extAuxRegister name,address,mode

The ARCtangent A4 has extensible auxiliary register space. The auxiliary registers can be defined in the assembler source code by using this directive. The first parameter is the name of the new auxiallry register. The second parameter is the address of the register in the auxiliary register memory map for the variant of the ARC. The third parameter specifies the mode in which the register can be operated is and it can be one of:

r (readonly)

w (write only)

r|w (read or write)

For example:

.extAuxRegister mulhi,0x12,w

This specifies an extension auxiliary register called mulhi which is at address 0x12 in the memory space and which is only writable.

.extCondCode suffix,value

The condition codes on the ARCtangent A4 are extensible and can be specified by means of this assembler directive. They are specified by the suffix and the value for the condition code. They can be used to specify extra condition codes with any values. For example:

.extCondCode is_busy,0x14 add.is_busy r1,r2,r3 bis_busy _main

.extCoreRegister name,regnum,mode,shortcut

Specifies an extension core register name for the application. This allows a register name with a valid regnum between 0 and 60, with the following as valid values for mode

`r (readonly)'

`w (write only)'

`r|w (read or write)'

The other parameter gives a description of the register having a shortcut in the pipeline. The valid values are:

can_shortcut

cannot_shortcut

For example:

.extCoreRegister mlo,57,r,can_shortcut

This defines an extension core register mlo with the value 57 which can shortcut the pipeline.

.extInstruction name,opcode,subopcode,suffixclass,syntaxclass

The ARCtangent A4 allows the user to specify extension instructions. The extension instructions are not macros. The assembler creates encodings for use of these instructions according to the specification by the user. The parameters are:

@bullet{name}

Name of the extension instruction

@bullet{opcode}

Opcode to be used. (Bits 27:31 in the encoding). Valid values 0x10-0x1f or 0x03

@bullet{subopcode}

Subopcode to be used. Valid values are from 0x09-0x3f. However the correct value also depends on syntaxclass

@bullet{suffixclass}

Determines the kinds of suffixes to be allowed. Valid values are SUFFIX_NONE, SUFFIX_COND, SUFFIX_FLAG which indicates the absence or presence of conditional suffixes and flag setting by the extension instruction. It is also possible to specify that an instruction sets the flags and is conditional by using SUFFIX_CODE | SUFFIX_FLAG.

@bullet{syntaxclass}

Determines the syntax class for the instruction. It can have the following values:

SYNTAX_2OP:

2 Operand Instruction

SYNTAX_3OP:

3 Operand Instruction

In addition there could be modifiers for the syntax class as described below:

Syntax Class Modifiers are:
• OP1_MUST_BE_IMM: Modifies syntax class SYNTAX_3OP, specifying that the first operand of a three-operand instruction must be an immediate (i.e., the result is discarded). OP1_MUST_BE_IMM is used by bitwise ORing it with SYNTAX_3OP as given in the example below. This could usually be used to set the flags using specific instructions and not retain results.

• OP1_IMM_IMPLIED: Modifies syntax class SYNTAX_20P, it specifies that there is an implied immediate destination operand which does not appear in the syntax. For example, if the source code contains an instruction like:

  inst r1,r2

  it really means that the first argument is an implied immediate (that is, the result is discarded). This is the same as though the source code were: inst 0,r1,r2. You use OP1_IMM_IMPLIED by bitwise ORing it with SYNTAX_20P.

For example, defining 64-bit multiplier with immediate operands:

.extInstruction mp64,0x14,0x0,SUFFIX_COND | SUFFIX_FLAG , SYNTAX_3OP|OP1_MUST_BE_IMM

The above specifies an extension instruction called mp64 which has 3 operands, sets the flags, can be used with a condition code, for which the first operand is an immediate. (Equivalent to discarding the result of the operation).

.extInstruction mul64,0x14,0x00,SUFFIX_COND, SYNTAX_2OP|OP1_IMM_IMPLIED

This describes a 2 operand instruction with an implicit first immediate operand. The result of this operation would be discarded.

.half expressions

*TODO*

.long expressions

*TODO*

.option arc|arc5|arc6|arc7|arc8

The .option directive must be followed by the desired core version. Again arc is an alias for arc6.

Note: the .option directive overrides the command line option -marc; a warning is emitted when the version is not consistent between the two - even for the implicit default core version (arc6).

.short expressions

*TODO*

.word expressions

*TODO*

9.2.5 Opcodes

For information on the ARC instruction set, see ARC Programmers Reference Manual, ARC International (www.arc.com)

9.3 ARM Dependent Features

9.3.1 Options
9.3.2 Syntax
9.3.3 Floating Point
9.3.4 ARM Machine Directives
9.3.5 Opcodes
9.3.6 Mapping Symbols
9.3.7 Unwinding

9.3.1 Options

-mcpu=processor[+extension...]

This option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are recognized: arm1, arm2, arm250, arm3, arm6, arm60, arm600, arm610, arm620, arm7, arm7m, arm7d, arm7dm, arm7di, arm7dmi, arm70, arm700, arm700i, arm710, arm710t, arm720, arm720t, arm740t, arm710c, arm7100, arm7500, arm7500fe, arm7t, arm7tdmi, arm7tdmi-s, arm8, arm810, strongarm, strongarm1, strongarm110, strongarm1100, strongarm1110, arm9, arm920, arm920t, arm922t, arm940t, arm9tdmi, fa526 (Faraday FA526 processor), fa626 (Faraday FA626 processor), arm9e, arm926e, arm926ej-s, arm946e-r0, arm946e, arm946e-s, arm966e-r0, arm966e, arm966e-s, arm968e-s, arm10t, arm10tdmi, arm10e, arm1020, arm1020t, arm1020e, arm1022e, arm1026ej-s, fa626te (Faraday FA626TE processor), fa726te (Faraday FA726TE processor), arm1136j-s, arm1136jf-s, arm1156t2-s, arm1156t2f-s, arm1176jz-s, arm1176jzf-s, mpcore, mpcorenovfp, cortex-a8, cortex-a9, cortex-r4, cortex-m3, cortex-m1, cortex-m0, ep9312 (ARM920 with Cirrus Maverick coprocessor), i80200 (Intel XScale processor) iwmmxt (Intel(r) XScale processor with Wireless MMX(tm) technology coprocessor) and xscale. The special name all may be used to allow the assembler to accept instructions valid for any ARM processor.

In addition to the basic instruction set, the assembler can be told to accept various extension mnemonics that extend the processor using the co-processor instruction space. For example, -mcpu=arm920+maverick is equivalent to specifying -mcpu=ep9312. The following extensions are currently supported: +maverick +iwmmxt and +xscale.

-march=architecture[+extension...]

This option specifies the target architecture. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target architecture. The following architecture names are recognized: armv1, armv2, armv2a, armv2s, armv3, armv3m, armv4, armv4xm, armv4t, armv4txm, armv5, armv5t, armv5txm, armv5te, armv5texp, armv6, armv6j, armv6k, armv6z, armv6zk, armv7, armv7-a, armv7-r, armv7-m, iwmmxt and xscale. If both -mcpu and -march are specified, the assembler will use the setting for -mcpu.

The architecture option can be extended with the same instruction set extension options as the -mcpu option.

-mfpu=floating-point-format

This option specifies the floating point format to assemble for. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target floating point unit. The following format options are recognized: softfpa, fpe, fpe2, fpe3, fpa, fpa10, fpa11, arm7500fe, softvfp, softvfp+vfp, vfp, vfp10, vfp10-r0, vfp9, vfpxd, vfpv2 vfpv3 vfpv3-d16 arm1020t, arm1020e, arm1136jf-s, maverick and neon.

In addition to determining which instructions are assembled, this option also affects the way in which the .double assembler directive behaves when assembling little-endian code.

The default is dependent on the processor selected. For Architecture 5 or later, the default is to assembler for VFP instructions; for earlier architectures the default is to assemble for FPA instructions.

-mthumb

This option specifies that the assembler should start assembling Thumb instructions; that is, it should behave as though the file starts with a .code 16 directive.

-mthumb-interwork

This option specifies that the output generated by the assembler should be marked as supporting interworking.

-mimplicit-it=never

-mimplicit-it=always

-mimplicit-it=arm

-mimplicit-it=thumb

The -mimplicit-it option controls the behavior of the assembler when conditional instructions are not enclosed in IT blocks. There are four possible behaviors. If never is specified, such constructs cause a warning in ARM code and an error in Thumb-2 code. If always is specified, such constructs are accepted in both ARM and Thumb-2 code, where the IT instruction is added implicitly. If arm is specified, such constructs are accepted in ARM code and cause an error in Thumb-2 code. If thumb is specified, such constructs cause a warning in ARM code and are accepted in Thumb-2 code. If you omit this option, the behavior is equivalent to -mimplicit-it=arm.

-mapcs [26|32]

This option specifies that the output generated by the assembler should be marked as supporting the indicated version of the Arm Procedure. Calling Standard.

-matpcs

This option specifies that the output generated by the assembler should be marked as supporting the Arm/Thumb Procedure Calling Standard. If enabled this option will cause the assembler to create an empty debugging section in the object file called .arm.atpcs. Debuggers can use this to determine the ABI being used by.

-mapcs-float

This indicates the floating point variant of the APCS should be used. In this variant floating point arguments are passed in FP registers rather than integer registers.

-mapcs-reentrant

This indicates that the reentrant variant of the APCS should be used. This variant supports position independent code.

-mfloat-abi=abi

This option specifies that the output generated by the assembler should be marked as using specified floating point ABI. The following values are recognized: soft, softfp and hard.

-meabi=ver

This option specifies which EABI version the produced object files should conform to. The following values are recognized: gnu, 4 and 5.

-EB

This option specifies that the output generated by the assembler should be marked as being encoded for a big-endian processor.

-EL

This option specifies that the output generated by the assembler should be marked as being encoded for a little-endian processor.

-k

This option specifies that the output of the assembler should be marked as position-independent code (PIC).

--fix-v4bx

Allow BX instructions in ARMv4 code. This is intended for use with the linker option of the same name.

-mwarn-deprecated

-mno-warn-deprecated

Enable or disable warnings about using deprecated options or features. The default is to warn.

9.3.2 Syntax

9.3.2.1 Instruction Set Syntax		Instruction Set
9.3.2.2 Special Characters
9.3.2.3 Register Names
9.3.3.1 ARM relocation generation		Relocations

9.3.2.1 Instruction Set Syntax

*

Immediate operands do not require a # prefix.

*

The IT instruction may appear, and if it does it is validated against subsequent conditional affixes. In ARM mode it does not generate machine code, in THUMB mode it does.

*

For ARM instructions the conditional affixes always appear at the end of the instruction. For THUMB instructions conditional affixes can be used, but only inside the scope of an IT instruction.

*

All of the instructions new to the V6T2 architecture (and later) are available. (Only a few such instructions can be written in the divided syntax).

*

The .N and .W suffixes are recognized and honored.

*

All instructions set the flags if and only if they have an s affix.

9.3.2.2 Special Characters

The presence of a `@' on a line indicates the start of a comment that extends to the end of the current line. If a `#' appears as the first character of a line, the whole line is treated as a comment.

The `;' character can be used instead of a newline to separate statements.

Either `#' or `$' can be used to indicate immediate operands.

*TODO* Explain about /data modifier on symbols.

9.3.2.3 Register Names

*TODO* Explain about ARM register naming, and the predefined names.

9.3.3 Floating Point

The ARM family uses IEEE floating-point numbers.

9.3.3.1 ARM relocation generation

Specific data relocations can be generated by putting the relocation name in parentheses after the symbol name. For example:

.word foo(TARGET1)

This will generate an `R_ARM_TARGET1' relocation against the symbol foo. The following relocations are supported: GOT, GOTOFF, TARGET1, TARGET2, SBREL, TLSGD, TLSLDM, TLSLDO, GOTTPOFF and TPOFF.

For compatibility with older toolchains the assembler also accepts (PLT) after branch targets. This will generate the deprecated `R_ARM_PLT32' relocation.

Relocations for `MOVW' and `MOVT' instructions can be generated by prefixing the value with `#:lower16:' and `#:upper16' respectively. For example to load the 32-bit address of foo into r0:

MOVW r0, #:lower16:foo MOVT r0, #:upper16:foo

9.3.4 ARM Machine Directives

.2byte expression [, expression]*

.4byte expression [, expression]*

.8byte expression [, expression]*

These directives write 2, 4 or 8 byte values to the output section.

.align expression [, expression]

This is the generic .align directive. For the ARM however if the first argument is zero (ie no alignment is needed) the assembler will behave as if the argument had been 2 (ie pad to the next four byte boundary). This is for compatibility with ARM's own assembler.

.arch name

Select the target architecture. Valid values for name are the same as for the `-march' commandline option.

.arm

This performs the same action as .code 32.

.pad #count

Generate unwinder annotations for a stack adjustment of count bytes. A positive value indicates the function prologue allocated stack space by decrementing the stack pointer.

.bss

This directive switches to the .bss section.

.cantunwind

Prevents unwinding through the current function. No personality routine or exception table data is required or permitted.

.code [16|32]

This directive selects the instruction set being generated. The value 16 selects Thumb, with the value 32 selecting ARM.

.cpu name

Select the target processor. Valid values for name are the same as for the `-mcpu' commandline option.

name .dn register name [.type] [[index]]

name .qn register name [.type] [[index]]

The dn and qn directives are used to create typed and/or indexed register aliases for use in Advanced SIMD Extension (Neon) instructions. The former should be used to create aliases of double-precision registers, and the latter to create aliases of quad-precision registers.

If these directives are used to create typed aliases, those aliases can be used in Neon instructions instead of writing types after the mnemonic or after each operand. For example:

x .dn d2.f32 y .dn d3.f32 z .dn d4.f32[1] vmul x,y,z

This is equivalent to writing the following:

vmul.f32 d2,d3,d4[1]

Aliases created using dn or qn can be destroyed using unreq.

.eabi_attribute tag, value

Set the EABI object attribute tag to value.

The tag is either an attribute number, or one of the following: Tag_CPU_raw_name, Tag_CPU_name, Tag_CPU_arch, Tag_CPU_arch_profile, Tag_ARM_ISA_use, Tag_THUMB_ISA_use, Tag_VFP_arch, Tag_WMMX_arch, Tag_Advanced_SIMD_arch, Tag_PCS_config, Tag_ABI_PCS_R9_use, Tag_ABI_PCS_RW_data, Tag_ABI_PCS_RO_data, Tag_ABI_PCS_GOT_use, Tag_ABI_PCS_wchar_t, Tag_ABI_FP_rounding, Tag_ABI_FP_denormal, Tag_ABI_FP_exceptions, Tag_ABI_FP_user_exceptions, Tag_ABI_FP_number_model, Tag_ABI_align8_needed, Tag_ABI_align8_preserved, Tag_ABI_enum_size, Tag_ABI_HardFP_use, Tag_ABI_VFP_args, Tag_ABI_WMMX_args, Tag_ABI_optimization_goals, Tag_ABI_FP_optimization_goals, Tag_compatibility, Tag_CPU_unaligned_access, Tag_VFP_HP_extension, Tag_ABI_FP_16bit_format, Tag_nodefaults, Tag_also_compatible_with, Tag_conformance, Tag_T2EE_use, Tag_Virtualization_use, Tag_MPextension_use

The value is either a number, "string", or number, "string" depending on the tag.

.even

This directive aligns to an even-numbered address.

.extend expression [, expression]*

.ldouble expression [, expression]*

These directives write 12byte long double floating-point values to the output section. These are not compatible with current ARM processors or ABIs.

.fnend

Marks the end of a function with an unwind table entry. The unwind index table entry is created when this directive is processed.

If no personality routine has been specified then standard personality routine 0 or 1 will be used, depending on the number of unwind opcodes required.

.fnstart

Marks the start of a function with an unwind table entry.

.force_thumb

This directive forces the selection of Thumb instructions, even if the target processor does not support those instructions

.fpu name

Select the floating-point unit to assemble for. Valid values for name are the same as for the `-mfpu' commandline option.

.handlerdata

Marks the end of the current function, and the start of the exception table entry for that function. Anything between this directive and the .fnend directive will be added to the exception table entry.

Must be preceded by a .personality or .personalityindex directive.

.inst opcode [ , ... ]

.inst.n opcode [ , ... ]

.inst.w opcode [ , ... ]

Generates the instruction corresponding to the numerical value opcode. .inst.n and .inst.w allow the Thumb instruction size to be specified explicitly, overriding the normal encoding rules.

.ldouble expression [, expression]*

See .extend.

.ltorg

This directive causes the current contents of the literal pool to be dumped into the current section (which is assumed to be the .text section) at the current location (aligned to a word boundary). GAS maintains a separate literal pool for each section and each sub-section. The .ltorg directive will only affect the literal pool of the current section and sub-section. At the end of assembly all remaining, un-empty literal pools will automatically be dumped.

Note - older versions of GAS would dump the current literal pool any time a section change occurred. This is no longer done, since it prevents accurate control of the placement of literal pools.

.movsp reg [, #offset]

Tell the unwinder that reg contains an offset from the current stack pointer. If offset is not specified then it is assumed to be zero.

.object_arch name

Override the architecture recorded in the EABI object attribute section. Valid values for name are the same as for the .arch directive. Typically this is useful when code uses runtime detection of CPU features.

.packed expression [, expression]*

This directive writes 12-byte packed floating-point values to the output section. These are not compatible with current ARM processors or ABIs.

.pad #count

Generate unwinder annotations for a stack adjustment of count bytes. A positive value indicates the function prologue allocated stack space by decrementing the stack pointer.

.personality name

Sets the personality routine for the current function to name.

.personalityindex index

Sets the personality routine for the current function to the EABI standard routine number index

.pool

This is a synonym for .ltorg.

name .req register name

This creates an alias for register name called name. For example:

foo .req r0

.save reglist

Generate unwinder annotations to restore the registers in reglist. The format of reglist is the same as the corresponding store-multiple instruction.

core registers .save {r4, r5, r6, lr} stmfd sp!, {r4, r5, r6, lr} FPA registers .save f4, 2 sfmfd f4, 2, [sp]! VFP registers .save {d8, d9, d10} fstmdx sp!, {d8, d9, d10} iWMMXt registers .save {wr10, wr11} wstrd wr11, [sp, #-8]! wstrd wr10, [sp, #-8]! or .save wr11 wstrd wr11, [sp, #-8]! .save wr10 wstrd wr10, [sp, #-8]!

.setfp fpreg, spreg [, #offset]

Make all unwinder annotations relative to a frame pointer. Without this the unwinder will use offsets from the stack pointer.

The syntax of this directive is the same as the sub or mov instruction used to set the frame pointer. spreg must be either sp or mentioned in a previous .movsp directive.

.movsp ip mov ip, sp ... .setfp fp, ip, #4 sub fp, ip, #4

.secrel32 expression [, expression]*

This directive emits relocations that evaluate to the section-relative offset of each expression's symbol. This directive is only supported for PE targets.

.syntax [unified | divided]

This directive sets the Instruction Set Syntax as described in the 9.3.2.1 Instruction Set Syntax section.

.thumb

This performs the same action as .code 16.

.thumb_func

This directive specifies that the following symbol is the name of a Thumb encoded function. This information is necessary in order to allow the assembler and linker to generate correct code for interworking between Arm and Thumb instructions and should be used even if interworking is not going to be performed. The presence of this directive also implies .thumb

This directive is not neccessary when generating EABI objects. On these targets the encoding is implicit when generating Thumb code.

.thumb_set

This performs the equivalent of a .set directive in that it creates a symbol which is an alias for another symbol (possibly not yet defined). This directive also has the added property in that it marks the aliased symbol as being a thumb function entry point, in the same way that the .thumb_func directive does.

.unreq alias-name

This undefines a register alias which was previously defined using the req, dn or qn directives. For example:

foo .req r0 .unreq foo

An error occurs if the name is undefined. Note - this pseudo op can be used to delete builtin in register name aliases (eg 'r0'). This should only be done if it is really necessary.

.unwind_raw offset, byte1, ...

Insert one of more arbitary unwind opcode bytes, which are known to adjust the stack pointer by offset bytes.

For example .unwind_raw 4, 0xb1, 0x01 is equivalent to .save {r0}

.vsave vfp-reglist

Generate unwinder annotations to restore the VFP registers in vfp-reglist using FLDMD. Also works for VFPv3 registers that are to be restored using VLDM. The format of vfp-reglist is the same as the corresponding store-multiple instruction.

VFP registers .vsave {d8, d9, d10} fstmdd sp!, {d8, d9, d10} VFPv3 registers .vsave {d15, d16, d17} vstm sp!, {d15, d16, d17}

Since FLDMX and FSTMX are now deprecated, this directive should be used in favour of .save for saving VFP registers for ARMv6 and above.

9.3.5 Opcodes

as implements all the standard ARM opcodes. It also implements several pseudo opcodes, including several synthetic load instructions.

NOP

nop

This pseudo op will always evaluate to a legal ARM instruction that does nothing. Currently it will evaluate to MOV r0, r0.

LDR

ldr <register> , = <expression>

If expression evaluates to a numeric constant then a MOV or MVN instruction will be used in place of the LDR instruction, if the constant can be generated by either of these instructions. Otherwise the constant will be placed into the nearest literal pool (if it not already there) and a PC relative LDR instruction will be generated.

ADR

adr <register> <label>

This instruction will load the address of label into the indicated register. The instruction will evaluate to a PC relative ADD or SUB instruction depending upon where the label is located. If the label is out of range, or if it is not defined in the same file (and section) as the ADR instruction, then an error will be generated. This instruction will not make use of the literal pool.

ADRL

adrl <register> <label>

This instruction will load the address of label into the indicated register. The instruction will evaluate to one or two PC relative ADD or SUB instructions depending upon where the label is located. If a second instruction is not needed a NOP instruction will be generated in its place, so that this instruction is always 8 bytes long.

If the label is out of range, or if it is not defined in the same file (and section) as the ADRL instruction, then an error will be generated. This instruction will not make use of the literal pool.

For information on the ARM or Thumb instruction sets, see ARM Software Development Toolkit Reference Manual, Advanced RISC Machines Ltd.

9.3.6 Mapping Symbols

The ARM ELF specification requires that special symbols be inserted into object files to mark certain features:

$a

At the start of a region of code containing ARM instructions.

$t

At the start of a region of code containing THUMB instructions.

$d

At the start of a region of data.

The assembler will automatically insert these symbols for you - there is no need to code them yourself. Support for tagging symbols ($b, $f, $p and $m) which is also mentioned in the current ARM ELF specification is not implemented. This is because they have been dropped from the new EABI and so tools cannot rely upon their presence.

9.3.7 Unwinding

The ABI for the ARM Architecture specifies a standard format for exception unwind information. This information is used when an exception is thrown to determine where control should be transferred. In particular, the unwind information is used to determine which function called the function that threw the exception, and which function called that one, and so forth. This information is also used to restore the values of callee-saved registers in the function catching the exception.

If you are writing functions in assembly code, and those functions call other functions that throw exceptions, you must use assembly pseudo ops to ensure that appropriate exception unwind information is generated. Otherwise, if one of the functions called by your assembly code throws an exception, the run-time library will be unable to unwind the stack through your assembly code and your program will not behave correctly.

To illustrate the use of these pseudo ops, we will examine the code that G++ generates for the following C++ input:

@verbatim void callee (int *);

int caller () { int i; callee (&i); return i; }

This example does not show how to throw or catch an exception from assembly code. That is a much more complex operation and should always be done in a high-level language, such as C++, that directly supports exceptions.

The code generated by one particular version of G++ when compiling the example above is:

@verbatim _Z6callerv: .fnstart .LFB2: Function supports interworking. args = 0, pretend = 0, frame = 8 frame_needed = 1, uses_anonymous_args = 0 stmfd sp!, {fp, lr} .save {fp, lr} .LCFI0: .setfp fp, sp, #4 add fp, sp, #4 .LCFI1: .pad #8 sub sp, sp, #8 .LCFI2: sub r3, fp, #8 mov r0, r3 bl _Z6calleePi ldr r3, [fp, #-8] mov r0, r3 sub sp, fp, #4 ldmfd sp!, {fp, lr} bx lr .LFE2: .fnend

Of course, the sequence of instructions varies based on the options you pass to GCC and on the version of GCC in use. The exact instructions are not important since we are focusing on the pseudo ops that are used to generate unwind information.

An important assumption made by the unwinder is that the stack frame does not change during the body of the function. In particular, since we assume that the assembly code does not itself throw an exception, the only point where an exception can be thrown is from a call, such as the bl instruction above. At each call site, the same saved registers (including lr, which indicates the return address) must be located in the same locations relative to the frame pointer.

The .fnstart (see section .fnstart pseudo op) pseudo op appears immediately before the first instruction of the function while the .fnend (see section .fnend pseudo op) pseudo op appears immediately after the last instruction of the function. These pseudo ops specify the range of the function.

Only the order of the other pseudos ops (e.g., .setfp or .pad) matters; their exact locations are irrelevant. In the example above, the compiler emits the pseudo ops with particular instructions. That makes it easier to understand the code, but it is not required for correctness. It would work just as well to emit all of the pseudo ops other than .fnend in the same order, but immediately after .fnstart.

The .save (see section .save pseudo op) pseudo op indicates registers that have been saved to the stack so that they can be restored before the function returns. The argument to the .save pseudo op is a list of registers to save. If a register is "callee-saved" (as specified by the ABI) and is modified by the function you are writing, then your code must save the value before it is modified and restore the original value before the function returns. If an exception is thrown, the run-time library restores the values of these registers from their locations on the stack before returning control to the exception handler. (Of course, if an exception is not thrown, the function that contains the .save pseudo op restores these registers in the function epilogue, as is done with the ldmfd instruction above.)

You do not have to save callee-saved registers at the very beginning of the function and you do not need to use the .save pseudo op immediately following the point at which the registers are saved. However, if you modify a callee-saved register, you must save it on the stack before modifying it and before calling any functions which might throw an exception. And, you must use the .save pseudo op to indicate that you have done so.

The .pad (see section .pad) pseudo op indicates a modification of the stack pointer that does not save any registers. The argument is the number of bytes (in decimal) that are subtracted from the stack pointer. (On ARM CPUs, the stack grows downwards, so subtracting from the stack pointer increases the size of the stack.)

The .setfp (see section .setfp pseudo op) pseudo op indicates the register that contains the frame pointer. The first argument is the register that is set, which is typically fp. The second argument indicates the register from which the frame pointer takes its value. The third argument, if present, is the value (in decimal) added to the register specified by the second argument to compute the value of the frame pointer. You should not modify the frame pointer in the body of the function.

If you do not use a frame pointer, then you should not use the .setfp pseudo op. If you do not use a frame pointer, then you should avoid modifying the stack pointer outside of the function prologue. Otherwise, the run-time library will be unable to find saved registers when it is unwinding the stack.

The pseudo ops described above are sufficient for writing assembly code that calls functions which may throw exceptions. If you need to know more about the object-file format used to represent unwind information, you may consult the Exception Handling ABI for the ARM Architecture available from http://infocenter.arm.com.

9.4 AVR Dependent Features

9.4.1 Options
9.4.2 Syntax
9.4.3 Opcodes

9.4.1 Options

-mmcu=mcu

Specify ATMEL AVR instruction set or MCU type.

Instruction set avr1 is for the minimal AVR core, not supported by the C compiler, only for assembler programs (MCU types: at90s1200, attiny11, attiny12, attiny15, attiny28).

Instruction set avr2 (default) is for the classic AVR core with up to 8K program memory space (MCU types: at90s2313, at90s2323, at90s2333, at90s2343, attiny22, attiny26, at90s4414, at90s4433, at90s4434, at90s8515, at90c8534, at90s8535).

Instruction set avr25 is for the classic AVR core with up to 8K program memory space plus the MOVW instruction (MCU types: attiny13, attiny13a, attiny2313, attiny2313a, attiny24, attiny24a, attiny4313, attiny44, attiny44a, attiny84, attiny25, attiny45, attiny85, attiny261, attiny261a, attiny461, attiny861, attiny861a, attiny87, attiny43u, attiny48, attiny88, at86rf401, ata6289).

Instruction set avr3 is for the classic AVR core with up to 128K program memory space (MCU types: at43usb355, at76c711).

Instruction set avr31 is for the classic AVR core with exactly 128K program memory space (MCU types: atmega103, at43usb320).

Instruction set avr35 is for classic AVR core plus MOVW, CALL, and JMP instructions (MCU types: attiny167, attiny327, at90usb82, at90usb162, atmega8u2, atmega16u2, atmega32u2).

Instruction set avr4 is for the enhanced AVR core with up to 8K program memory space (MCU types: atmega48, atmega48p,atmega8, atmega88, atmega88p, atmega8515, atmega8535, atmega8hva, atmega4hvd, atmega8hvd, at90pwm1, at90pwm2, at90pwm2b, at90pwm3, at90pwm3b, at90pwm81, atmega8m1, atmega8c1).

Instruction set avr5 is for the enhanced AVR core with up to 128K program memory space (MCU types: atmega16, atmega161, atmega162, atmega163, atmega164p, atmega165, atmega165p, atmega168, atmega168p, atmega169, atmega169p, atmega16c1, atmega32, atmega323, atmega324p, atmega325, atmega325p, atmega3250, atmega3250p, atmega328p, atmega329, atmega329p, atmega3290, atmega3290p, atmega406, atmega64, atmega640, atmega644, atmega644p, atmega644pa, atmega645, atmega6450, atmega649, atmega6490, atmega16hva, atmega16hvb, atmega32hvb, at90can32, at90can64, at90pwm216, at90pwm316, atmega32c1, atmega64c1, atmega16m1, atmega32m1, atmega64m1, atmega16u4, atmega32u4, atmega32u6, at90usb646, at90usb647, at94k, at90scr100).

Instruction set avr51 is for the enhanced AVR core with exactly 128K program memory space (MCU types: atmega128, atmega1280, atmega1281, atmega1284p, atmega128rfa1, at90can128, at90usb1286, at90usb1287, m3000f, m3000s, m3001b).

Instruction set avr6 is for the enhanced AVR core with a 3-byte PC (MCU types: atmega2560, atmega2561).

-mall-opcodes

Accept all AVR opcodes, even if not supported by -mmcu.

-mno-skip-bug

This option disable warnings for skipping two-word instructions.

-mno-wrap

This option reject rjmp/rcall instructions with 8K wrap-around.

9.4.2 Syntax

9.4.2.1 Special Characters
9.4.2.2 Register Names
9.4.2.3 Relocatable Expression Modifiers

9.4.2.1 Special Characters

The presence of a `;' on a line indicates the start of a comment that extends to the end of the current line. If a `#' appears as the first character of a line, the whole line is treated as a comment.

The `$' character can be used instead of a newline to separate statements.

9.4.2.2 Register Names

The AVR has 32 x 8-bit general purpose working registers `r0', `r1', ... `r31'. Six of the 32 registers can be used as three 16-bit indirect address register pointers for Data Space addressing. One of the these address pointers can also be used as an address pointer for look up tables in Flash program memory. These added function registers are the 16-bit `X', `Y' and `Z' - registers.

X = r26:r27 Y = r28:r29 Z = r30:r31

9.4.2.3 Relocatable Expression Modifiers

The assembler supports several modifiers when using relocatable addresses in AVR instruction operands. The general syntax is the following:

modifier(relocatable-expression)

lo8

This modifier allows you to use bits 0 through 7 of an address expression as 8 bit relocatable expression.

hi8

This modifier allows you to use bits 7 through 15 of an address expression as 8 bit relocatable expression. This is useful with, for example, the AVR `ldi' instruction and `lo8' modifier.

For example

ldi r26, lo8(sym+10) ldi r27, hi8(sym+10)

hh8

This modifier allows you to use bits 16 through 23 of an address expression as 8 bit relocatable expression. Also, can be useful for loading 32 bit constants.

hlo8

Synonym of `hh8'.

hhi8

This modifier allows you to use bits 24 through 31 of an expression as 8 bit expression. This is useful with, for example, the AVR `ldi' instruction and `lo8', `hi8', `hlo8', `hhi8', modifier.

For example

ldi r26, lo8(285774925) ldi r27, hi8(285774925) ldi r28, hlo8(285774925) ldi r29, hhi8(285774925) ; r29,r28,r27,r26 = 285774925

pm_lo8

This modifier allows you to use bits 0 through 7 of an address expression as 8 bit relocatable expression. This modifier useful for addressing data or code from Flash/Program memory. The using of `pm_lo8' similar to `lo8'.

pm_hi8

This modifier allows you to use bits 8 through 15 of an address expression as 8 bit relocatable expression. This modifier useful for addressing data or code from Flash/Program memory.

pm_hh8

This modifier allows you to use bits 15 through 23 of an address expression as 8 bit relocatable expression. This modifier useful for addressing data or code from Flash/Program memory.

9.4.3 Opcodes

For detailed information on the AVR machine instruction set, see www.atmel.com/products/AVR.

as implements all the standard AVR opcodes. The following table summarizes the AVR opcodes, and their arguments.

Legend: r any register d `ldi' register (r16-r31) v `movw' even register (r0, r2, ..., r28, r30) a `fmul' register (r16-r23) w `adiw' register (r24,r26,r28,r30) e pointer registers (X,Y,Z) b base pointer register and displacement ([YZ]+disp) z Z pointer register (for [e]lpm Rd,Z[+]) M immediate value from 0 to 255 n immediate value from 0 to 255 ( n = ~M ). Relocation impossible s immediate value from 0 to 7 P Port address value from 0 to 63. (in, out) p Port address value from 0 to 31. (cbi, sbi, sbic, sbis) K immediate value from 0 to 63 (used in `adiw', `sbiw') i immediate value l signed pc relative offset from -64 to 63 L signed pc relative offset from -2048 to 2047 h absolute code address (call, jmp) S immediate value from 0 to 7 (S = s << 4) ? use this opcode entry if no parameters, else use next opcode entry 1001010010001000 clc 1001010011011000 clh 1001010011111000 cli 1001010010101000 cln 1001010011001000 cls 1001010011101000 clt 1001010010111000 clv 1001010010011000 clz 1001010000001000 sec 1001010001011000 seh 1001010001111000 sei 1001010000101000 sen 1001010001001000 ses 1001010001101000 set 1001010000111000 sev 1001010000011000 sez 100101001SSS1000 bclr S 100101000SSS1000 bset S 1001010100001001 icall 1001010000001001 ijmp 1001010111001000 lpm ? 1001000ddddd010+ lpm r,z 1001010111011000 elpm ? 1001000ddddd011+ elpm r,z 0000000000000000 nop 1001010100001000 ret 1001010100011000 reti 1001010110001000 sleep 1001010110011000 break 1001010110101000 wdr 1001010111101000 spm 000111rdddddrrrr adc r,r 000011rdddddrrrr add r,r 001000rdddddrrrr and r,r 000101rdddddrrrr cp r,r 000001rdddddrrrr cpc r,r 000100rdddddrrrr cpse r,r 001001rdddddrrrr eor r,r 001011rdddddrrrr mov r,r 100111rdddddrrrr mul r,r 001010rdddddrrrr or r,r 000010rdddddrrrr sbc r,r 000110rdddddrrrr sub r,r 001001rdddddrrrr clr r 000011rdddddrrrr lsl r 000111rdddddrrrr rol r 001000rdddddrrrr tst r 0111KKKKddddKKKK andi d,M 0111KKKKddddKKKK cbr d,n 1110KKKKddddKKKK ldi d,M 11101111dddd1111 ser d 0110KKKKddddKKKK ori d,M 0110KKKKddddKKKK sbr d,M 0011KKKKddddKKKK cpi d,M 0100KKKKddddKKKK sbci d,M 0101KKKKddddKKKK subi d,M 1111110rrrrr0sss sbrc r,s 1111111rrrrr0sss sbrs r,s 1111100ddddd0sss bld r,s 1111101ddddd0sss bst r,s 10110PPdddddPPPP in r,P 10111PPrrrrrPPPP out P,r 10010110KKddKKKK adiw w,K 10010111KKddKKKK sbiw w,K 10011000pppppsss cbi p,s 10011010pppppsss sbi p,s 10011001pppppsss sbic p,s 10011011pppppsss sbis p,s 111101lllllll000 brcc l 111100lllllll000 brcs l 111100lllllll001 breq l 111101lllllll100 brge l 111101lllllll101 brhc l 111100lllllll101 brhs l 111101lllllll111 brid l 111100lllllll111 brie l 111100lllllll000 brlo l 111100lllllll100 brlt l 111100lllllll010 brmi l 111101lllllll001 brne l 111101lllllll010 brpl l 111101lllllll000 brsh l 111101lllllll110 brtc l 111100lllllll110 brts l 111101lllllll011 brvc l 111100lllllll011 brvs l 111101lllllllsss brbc s,l 111100lllllllsss brbs s,l 1101LLLLLLLLLLLL rcall L 1100LLLLLLLLLLLL rjmp L 1001010hhhhh111h call h 1001010hhhhh110h jmp h 1001010rrrrr0101 asr r 1001010rrrrr0000 com r 1001010rrrrr1010 dec r 1001010rrrrr0011 inc r 1001010rrrrr0110 lsr r 1001010rrrrr0001 neg r 1001000rrrrr1111 pop r 1001001rrrrr1111 push r 1001010rrrrr0111 ror r 1001010rrrrr0010 swap r 00000001ddddrrrr movw v,v 00000010ddddrrrr muls d,d 000000110ddd0rrr mulsu a,a 000000110ddd1rrr fmul a,a 000000111ddd0rrr fmuls a,a 000000111ddd1rrr fmulsu a,a 1001001ddddd0000 sts i,r 1001000ddddd0000 lds r,i 10o0oo0dddddbooo ldd r,b 100!000dddddee-+ ld r,e 10o0oo1rrrrrbooo std b,r 100!001rrrrree-+ st e,r 1001010100011001 eicall 1001010000011001 eijmp

9.5 Blackfin Dependent Features

9.5.1 Options		Blackfin Options
9.5.2 Syntax		Blackfin Syntax
9.5.3 Directives		Blackfin Directives

9.5.1 Options

-mcpu=processor[-sirevision]

This option specifies the target processor. The optional sirevision is not used in assembler. It's here such that GCC can easily pass down its -mcpu= option. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are recognized: bf512, bf514, bf516, bf518, bf522, bf523, bf524, bf525, bf526, bf527, bf531, bf532, bf533, bf534, bf535 (not implemented yet), bf536, bf537, bf538, bf539, bf542, bf542m, bf544, bf544m, bf547, bf547m, bf548, bf548m, bf549, bf549m, and bf561.

9.5.2 Syntax

Special Characters

Assembler input is free format and may appear anywhere on the line. One instruction may extend across multiple lines or more than one instruction may appear on the same line. White space (space, tab, comments or newline) may appear anywhere between tokens. A token must not have embedded spaces. Tokens include numbers, register names, keywords, user identifiers, and also some multicharacter special symbols like "+=", "/*" or "||".

Instruction Delimiting

A semicolon must terminate every instruction. Sometimes a complete instruction will consist of more than one operation. There are two cases where this occurs. The first is when two general operations are combined. Normally a comma separates the different parts, as in

a0= r3.h * r2.l, a1 = r3.l * r2.h ;

The second case occurs when a general instruction is combined with one or two memory references for joint issue. The latter portions are set off by a "||" token.

a0 = r3.h * r2.l || r1 = [p3++] || r4 = [i2++];

Register Names

The assembler treats register names and instruction keywords in a case insensitive manner. User identifiers are case sensitive. Thus, R3.l, R3.L, r3.l and r3.L are all equivalent input to the assembler.

Register names are reserved and may not be used as program identifiers.

Some operations (such as "Move Register") require a register pair. Register pairs are always data registers and are denoted using a colon, eg., R3:2. The larger number must be written firsts. Note that the hardware only supports odd-even pairs, eg., R7:6, R5:4, R3:2, and R1:0.

Some instructions (such as --SP (Push Multiple)) require a group of adjacent registers. Adjacent registers are denoted in the syntax by the range enclosed in parentheses and separated by a colon, eg., (R7:3). Again, the larger number appears first.

Portions of a particular register may be individually specified. This is written with a dot (".") following the register name and then a letter denoting the desired portion. For 32-bit registers, ".H" denotes the most significant ("High") portion. ".L" denotes the least-significant portion. The subdivisions of the 40-bit registers are described later.

Accumulators

The set of 40-bit registers A1 and A0 that normally contain data that is being manipulated. Each accumulator can be accessed in four ways.

one 40-bit register

The register will be referred to as A1 or A0.

one 32-bit register

The registers are designated as A1.W or A0.W.

two 16-bit registers

The registers are designated as A1.H, A1.L, A0.H or A0.L.

one 8-bit register

The registers are designated as A1.X or A0.X for the bits that extend beyond bit 31.

Data Registers

The set of 32-bit registers (R0, R1, R2, R3, R4, R5, R6 and R7) that normally contain data for manipulation. These are abbreviated as D-register or Dreg. Data registers can be accessed as 32-bit registers or as two independent 16-bit registers. The least significant 16 bits of each register is called the "low" half and is designated with ".L" following the register name. The most significant 16 bits are called the "high" half and is designated with ".H" following the name.

R7.L, r2.h, r4.L, R0.H

Pointer Registers

The set of 32-bit registers (P0, P1, P2, P3, P4, P5, SP and FP) that normally contain byte addresses of data structures. These are abbreviated as P-register or Preg.

p2, p5, fp, sp

Stack Pointer SP

The stack pointer contains the 32-bit address of the last occupied byte location in the stack. The stack grows by decrementing the stack pointer.

Frame Pointer FP

The frame pointer contains the 32-bit address of the previous frame pointer in the stack. It is located at the top of a frame.

Loop Top

LT0 and LT1. These registers contain the 32-bit address of the top of a zero overhead loop.

Loop Count

LC0 and LC1. These registers contain the 32-bit counter of the zero overhead loop executions.

Loop Bottom

LB0 and LB1. These registers contain the 32-bit address of the bottom of a zero overhead loop.

Index Registers

The set of 32-bit registers (I0, I1, I2, I3) that normally contain byte addresses of data structures. Abbreviated I-register or Ireg.

Modify Registers

The set of 32-bit registers (M0, M1, M2, M3) that normally contain offset values that are added and subracted to one of the index registers. Abbreviated as Mreg.

Length Registers

The set of 32-bit registers (L0, L1, L2, L3) that normally contain the length in bytes of the circular buffer. Abbreviated as Lreg. Clear the Lreg to disable circular addressing for the corresponding Ireg.

Base Registers

The set of 32-bit registers (B0, B1, B2, B3) that normally contain the base address in bytes of the circular buffer. Abbreviated as Breg.

Floating Point

The Blackfin family has no hardware floating point but the .float directive generates ieee floating point numbers for use with software floating point libraries.

Blackfin Opcodes

For detailed information on the Blackfin machine instruction set, see the Blackfin(r) Processor Instruction Set Reference.

9.5.3 Directives

The following directives are provided for compatibility with the VDSP assembler.

.byte2

Initializes a four byte data object.

.byte4

Initializes a two byte data object.

.db

TBD

.dd

TBD

.dw

TBD

.var

Define and initialize a 32 bit data object.

9.6 CR16 Dependent Features

9.6.1 CR16 Operand Qualifiers

CR16 Machine Operand Qualifiers

9.6.1 CR16 Operand Qualifiers

The National Semiconductor CR16 target of as has a few machine dependent operand qualifiers.

Operand expression type qualifier is an optional field in the instruction operand, to determines the type of the expression field of an operand. The @ is required. CR16 architecture uses one of the following expression qualifiers:

s

- Specifies expression operand type as small

m

- Specifies expression operand type as medium

l

- Specifies expression operand type as large

c

- Specifies the CR16 Assembler generates a relocation entry for the operand, where pc has implied bit, the expression is adjusted accordingly. The linker uses the relocation entry to update the operand address at link time.

got/GOT

- Specifies the CR16 Assembler generates a relocation entry for the operand, offset from Global Offset Table. The linker uses this relocation entry to update the operand address at link time

cgot/cGOT

- Specifies the CompactRISC Assembler generates a relocation entry for the operand, where pc has implied bit, the expression is adjusted accordingly. The linker uses the relocation entry to update the operand address at link time.

CR16 target operand qualifiers and its size (in bits):

`Immediate Operand'

- s ---- 4 bits

`'

- m ---- 16 bits, for movb and movw instructions.

`'

- m ---- 20 bits, movd instructions.

`'

- l ---- 32 bits

`Absolute Operand'

- s ---- Illegal specifier for this operand.

`'

- m ---- 20 bits, movd instructions.

`Displacement Operand'

- s ---- 8 bits

`'

- m ---- 16 bits

`'

- l ---- 24 bits

For example:

1 movw $_myfun@c,r1 This loads the address of _myfun, shifted right by 1, into r1. 2 movd $_myfun@c,(r2,r1) This loads the address of _myfun, shifted right by 1, into register-pair r2-r1. 3 _myfun_ptr: .long _myfun@c loadd _myfun_ptr, (r1,r0) jal (r1,r0) This .long directive, the address of _myfunc, shifted right by 1 at link time. 4 loadd _data1@GOT(r12), (r1,r0) This loads the address of _data1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r2-r1. 5 loadd _myfunc@cGOT(r12), (r1,r0) This loads the address of _myfun, shifted right by 1, into global offset table (ie GOT) and its offset value from GOT loads into register-pair r1-r0.

9.7 CRIS Dependent Features

9.7.1 Command-line Options
9.7.2 Instruction expansion
9.7.3 Symbols
9.7.4 Syntax

9.7.1 Command-line Options

The CRIS version of as has these machine-dependent command-line options.

The format of the generated object files can be either ELF or a.out, specified by the command-line options `--emulation=crisaout' and `--emulation=criself'. The default is ELF (criself), unless as has been configured specifically for a.out by using the configuration name cris-axis-aout.

There are two different link-incompatible ELF object file variants for CRIS, for use in environments where symbols are expected to be prefixed by a leading `_' character and for environments without such a symbol prefix. The variant used for GNU/Linux port has no symbol prefix. Which variant to produce is specified by either of the options `--underscore' and `--no-underscore'. The default is `--underscore'. Since symbols in CRIS a.out objects are expected to have a `_' prefix, specifying `--no-underscore' when generating a.out objects is an error. Besides the object format difference, the effect of this option is to parse register names differently (see crisnous). The `--no-underscore' option makes a `$' register prefix mandatory.

The option `--pic' must be passed to as in order to recognize the symbol syntax used for ELF (SVR4 PIC) position-independent-code (see crispic). This will also affect expansion of instructions. The expansion with `--pic' will use PC-relative rather than (slightly faster) absolute addresses in those expansions.

The option `--march=architecture' specifies the recognized instruction set and recognized register names. It also controls the architecture type of the object file. Valid values for architecture are:

v0_v10

All instructions and register names for any architecture variant in the set v0...v10 are recognized. This is the default if the target is configured as cris-*.

v10

Only instructions and register names for CRIS v10 (as found in ETRAX 100 LX) are recognized. This is the default if the target is configured as crisv10-*.

v32

Only instructions and register names for CRIS v32 (code name Guinness) are recognized. This is the default if the target is configured as crisv32-*. This value implies `--no-mul-bug-abort'. (A subsequent `--mul-bug-abort' will turn it back on.)

common_v10_v32

Only instructions with register names and addressing modes with opcodes common to the v10 and v32 are recognized.

When `-N' is specified, as will emit a warning when a 16-bit branch instruction is expanded into a 32-bit multiple-instruction construct (see section 9.7.2 Instruction expansion).

Some versions of the CRIS v10, for example in the Etrax 100 LX, contain a bug that causes destabilizing memory accesses when a multiply instruction is executed with certain values in the first operand just before a cache-miss. When the `--mul-bug-abort' command line option is active (the default value), as will refuse to assemble a file containing a multiply instruction at a dangerous offset, one that could be the last on a cache-line, or is in a section with insufficient alignment. This placement checking does not catch any case where the multiply instruction is dangerously placed because it is located in a delay-slot. The `--mul-bug-abort' command line option turns off the checking.

9.7.2 Instruction expansion

as will silently choose an instruction that fits the operand size for `[register+constant]' operands. For example, the offset 127 in move.d [r3+127],r4 fits in an instruction using a signed-byte offset. Similarly, move.d [r2+32767],r1 will generate an instruction using a 16-bit offset. For symbolic expressions and constants that do not fit in 16 bits including the sign bit, a 32-bit offset is generated.

For branches, as will expand from a 16-bit branch instruction into a sequence of instructions that can reach a full 32-bit address. Since this does not correspond to a single instruction, such expansions can optionally be warned about. See section 9.7.1 Command-line Options.

If the operand is found to fit the range, a lapc mnemonic will translate to a lapcq instruction. Use lapc.d to force the 32-bit lapc instruction.

Similarly, the addo mnemonic will translate to the shortest fitting instruction of addoq, addo.w and addo.d, when used with a operand that is a constant known at assembly time.

9.7.3 Symbols

Some symbols are defined by the assembler. They're intended to be used in conditional assembly, for example:

.if ..asm.arch.cris.v32 code for CRIS v32 .elseif ..asm.arch.cris.common_v10_v32 code common to CRIS v32 and CRIS v10 .elseif ..asm.arch.cris.v10 | ..asm.arch.cris.any_v0_v10 code for v10 .else .error "Code needs to be added here." .endif

These symbols are defined in the assembler, reflecting command-line options, either when specified or the default. They are always defined, to 0 or 1.

..asm.arch.cris.any_v0_v10

This symbol is non-zero when `--march=v0_v10' is specified or the default.

..asm.arch.cris.common_v10_v32

Set according to the option `--march=common_v10_v32'.

..asm.arch.cris.v10

Reflects the option `--march=v10'.

..asm.arch.cris.v32

Corresponds to `--march=v10'.

Speaking of symbols, when a symbol is used in code, it can have a suffix modifying its value for use in position-independent code. See section 9.7.4.2 Symbols in position-independent code.

9.7.4 Syntax

There are different aspects of the CRIS assembly syntax.

9.7.4.1 Special Characters
9.7.4.2 Symbols in position-independent code		Position-Independent Code Symbols
9.7.4.3 Register names		Register Names
9.7.4.4 Assembler Directives

9.7.4.1 Special Characters

The character `#' is a line comment character. It starts a comment if and only if it is placed at the beginning of a line.

A `;' character starts a comment anywhere on the line, causing all characters up to the end of the line to be ignored.

A `@' character is handled as a line separator equivalent to a logical new-line character (except in a comment), so separate instructions can be specified on a single line.

9.7.4.2 Symbols in position-independent code

When generating position-independent code (SVR4 PIC) for use in cris-axis-linux-gnu or crisv32-axis-linux-gnu shared libraries, symbol suffixes are used to specify what kind of run-time symbol lookup will be used, expressed in the object as different relocation types. Usually, all absolute symbol values must be located in a table, the global offset table, leaving the code position-independent; independent of values of global symbols and independent of the address of the code. The suffix modifies the value of the symbol, into for example an index into the global offset table where the real symbol value is entered, or a PC-relative value, or a value relative to the start of the global offset table. All symbol suffixes start with the character `:' (omitted in the list below). Every symbol use in code or a read-only section must therefore have a PIC suffix to enable a useful shared library to be created. Usually, these constructs must not be used with an additive constant offset as is usually allowed, i.e. no 4 as in symbol + 4 is allowed. This restriction is checked at link-time, not at assembly-time.

GOT

Attaching this suffix to a symbol in an instruction causes the symbol to be entered into the global offset table. The value is a 32-bit index for that symbol into the global offset table. The name of the corresponding relocation is `R_CRIS_32_GOT'. Example: move.d [$r0+extsym:GOT],$r9

GOT16

Same as for `GOT', but the value is a 16-bit index into the global offset table. The corresponding relocation is `R_CRIS_16_GOT'. Example: move.d [$r0+asymbol:GOT16],$r10

PLT

This suffix is used for function symbols. It causes a procedure linkage table, an array of code stubs, to be created at the time the shared object is created or linked against, together with a global offset table entry. The value is a pc-relative offset to the corresponding stub code in the procedure linkage table. This arrangement causes the run-time symbol resolver to be called to look up and set the value of the symbol the first time the function is called (at latest; depending environment variables). It is only safe to leave the symbol unresolved this way if all references are function calls. The name of the relocation is `R_CRIS_32_PLT_PCREL'. Example: add.d fnname:PLT,$pc

PLTG

Like PLT, but the value is relative to the beginning of the global offset table. The relocation is `R_CRIS_32_PLT_GOTREL'. Example: move.d fnname:PLTG,$r3

GOTPLT

Similar to `PLT', but the value of the symbol is a 32-bit index into the global offset table. This is somewhat of a mix between the effect of the `GOT' and the `PLT' suffix; the difference to `GOT' is that there will be a procedure linkage table entry created, and that the symbol is assumed to be a function entry and will be resolved by the run-time resolver as with `PLT'. The relocation is `R_CRIS_32_GOTPLT'. Example: jsr [$r0+fnname:GOTPLT]

GOTPLT16

A variant of `GOTPLT' giving a 16-bit value. Its relocation name is `R_CRIS_16_GOTPLT'. Example: jsr [$r0+fnname:GOTPLT16]

GOTOFF

This suffix must only be attached to a local symbol, but may be used in an expression adding an offset. The value is the address of the symbol relative to the start of the global offset table. The relocation name is `R_CRIS_32_GOTREL'. Example: move.d [$r0+localsym:GOTOFF],r3

9.7.4.3 Register names

A `$' character may always prefix a general or special register name in an instruction operand but is mandatory when the option `--no-underscore' is specified or when the .syntax register_prefix directive is in effect (see crisnous). Register names are case-insensitive.

9.7.4.4 Assembler Directives

There are a few CRIS-specific pseudo-directives in addition to the generic ones. See section 7. Assembler Directives. Constants emitted by pseudo-directives are in little-endian order for CRIS. There is no support for floating-point-specific directives for CRIS.

.dword EXPRESSIONS

The .dword directive is a synonym for .int, expecting zero or more EXPRESSIONS, separated by commas. For each expression, a 32-bit little-endian constant is emitted.

.syntax ARGUMENT

The .syntax directive takes as ARGUMENT one of the following case-sensitive choices.

no_register_prefix

The .syntax no_register_prefix directive makes a `$' character prefix on all registers optional. It overrides a previous setting, including the corresponding effect of the option `--no-underscore'. If this directive is used when ordinary symbols do not have a `_' character prefix, care must be taken to avoid ambiguities whether an operand is a register or a symbol; using symbols with names the same as general or special registers then invoke undefined behavior.

register_prefix

This directive makes a `$' character prefix on all registers mandatory. It overrides a previous setting, including the corresponding effect of the option `--underscore'.

leading_underscore

This is an assertion directive, emitting an error if the `--no-underscore' option is in effect.

no_leading_underscore

This is the opposite of the .syntax leading_underscore directive and emits an error if the option `--underscore' is in effect.

.arch ARGUMENT

This is an assertion directive, giving an error if the specified ARGUMENT is not the same as the specified or default value for the `--march=architecture' option (see march-option).

9.8 D10V Dependent Features

9.8.1 D10V Options
9.8.2 Syntax
9.8.3 Floating Point
9.8.4 Opcodes

9.8.1 D10V Options

`-O'

The D10V can often execute two sub-instructions in parallel. When this option is used, as will attempt to optimize its output by detecting when instructions can be executed in parallel.

`--nowarnswap'

To optimize execution performance, as will sometimes swap the order of instructions. Normally this generates a warning. When this option is used, no warning will be generated when instructions are swapped.

`--gstabs-packing'

`--no-gstabs-packing'

as packs adjacent short instructions into a single packed instruction. `--no-gstabs-packing' turns instruction packing off if `--gstabs' is specified as well; `--gstabs-packing' (the default) turns instruction packing on even when `--gstabs' is specified.

9.8.2 Syntax

The D10V syntax is based on the syntax in Mitsubishi's D10V architecture manual. The differences are detailed below.

9.8.2.1 Size Modifiers
9.8.2.2 Sub-Instructions
9.8.2.3 Special Characters
9.8.2.4 Register Names
9.8.2.5 Addressing Modes
9.8.2.6 @WORD Modifier

9.8.2.1 Size Modifiers

9.8.2.2 Sub-Instructions

If you do not want the assembler automatically making these decisions, you can control the packaging and execution type (parallel or sequential) with the special execution symbols described in the next section.

9.8.2.3 Special Characters

`->'

Sequential with instruction on the left first.

`<-'

Sequential with instruction on the right first.

`||'

Parallel

abs a1 -> abs r0

Execute these sequentially. The instruction on the right is in the right container and is executed second.

abs r0 <- abs a1

Execute these reverse-sequentially. The instruction on the right is in the right container, and is executed first.

ld2w r2,@r8+ || mac a0,r0,r7

Execute these in parallel.

ld2w r2,@r8+ ||

mac a0,r0,r7

Two-line format. Execute these in parallel.

ld2w r2,@r8+

mac a0,r0,r7

Two-line format. Execute these sequentially. Assembler will put them in the proper containers.

ld2w r2,@r8+ ->

mac a0,r0,r7

Two-line format. Execute these sequentially. Same as above but second instruction will always go into right container.

9.8.2.4 Register Names

Register Pairs

r0-r1

r2-r3

r4-r5

r6-r7

r8-r9

r10-r11

r12-r13

r14-r15

The D10V also has predefined symbols for these control registers and status bits:

psw

Processor Status Word

bpsw

Backup Processor Status Word

pc

Program Counter

bpc

Backup Program Counter

rpt_c

Repeat Count

rpt_s

Repeat Start address

rpt_e

Repeat End address

mod_s

Modulo Start address

mod_e

Modulo End address

iba

Instruction Break Address

f0

Flag 0

f1

Flag 1

c

Carry flag

9.8.2.5 Addressing Modes

Rn

Register direct

@Rn

Register indirect

@Rn+

Register indirect with post-increment

@Rn-

Register indirect with post-decrement

@-SP

Register indirect with pre-decrement

@(disp, Rn)

Register indirect with displacement

addr

PC relative address (for branch or rep).

#imm

Immediate data (the `#' is optional and ignored)

9.8.2.6 @WORD Modifier

ldi     r2, main@word
jmp     r2

9.8.3 Floating Point

9.8.4 Opcodes

9.9 D30V Dependent Features

9.9.1 D30V Options
9.9.2 Syntax
9.9.3 Floating Point
9.9.4 Opcodes

9.9.1 D30V Options

`-O'

The D30V can often execute two sub-instructions in parallel. When this option is used, as will attempt to optimize its output by detecting when instructions can be executed in parallel.

`-n'

When this option is used, as will issue a warning every time it adds a nop instruction.

`-N'

When this option is used, as will issue a warning if it needs to insert a nop after a 32-bit multiply before a load or 16-bit multiply instruction.

9.9.2 Syntax

The D30V syntax is based on the syntax in Mitsubishi's D30V architecture manual. The differences are detailed below.

9.9.2.1 Size Modifiers
9.9.2.2 Sub-Instructions
9.9.2.3 Special Characters
9.9.2.4 Guarded Execution
9.9.2.5 Register Names
9.9.2.6 Addressing Modes

9.9.2.1 Size Modifiers

9.9.2.2 Sub-Instructions

If you do not want the assembler automatically making these decisions, you can control the packaging and execution type (parallel or sequential) with the special execution symbols described in the next section.

9.9.2.3 Special Characters

To specify the executing order, use the following symbols:

`->'

Sequential with instruction on the left first.

`<-'

Sequential with instruction on the right first.

`||'

Parallel

The D30V syntax allows either one instruction per line, one instruction per line with the execution symbol, or two instructions per line. For example

abs r2,r3 -> abs r4,r5

Execute these sequentially. The instruction on the right is in the right container and is executed second.

abs r2,r3 <- abs r4,r5

Execute these reverse-sequentially. The instruction on the right is in the right container, and is executed first.

abs r2,r3 || abs r4,r5

Execute these in parallel.

ldw r2,@(r3,r4) ||

mulx r6,r8,r9

Two-line format. Execute these in parallel.

mulx a0,r8,r9

stw r2,@(r3,r4)

Two-line format. Execute these sequentially unless `-O' option is used. If the `-O' option is used, the assembler will determine if the instructions could be done in parallel (the above two instructions can be done in parallel), and if so, emit them as parallel instructions. The assembler will put them in the proper containers. In the above example, the assembler will put the `stw' instruction in left container and the `mulx' instruction in the right container.

stw r2,@(r3,r4) ->

mulx a0,r8,r9

Two-line format. Execute the `stw' instruction followed by the `mulx' instruction sequentially. The first instruction goes in the left container and the second instruction goes into right container. The assembler will give an error if the machine ordering constraints are violated.

stw r2,@(r3,r4) <-

mulx a0,r8,r9

Same as previous example, except that the `mulx' instruction is executed before the `stw' instruction.

Since `$' has no special meaning, you may use it in symbol names.

9.9.2.4 Guarded Execution

`/tx'

Execute the instruction if flag f0 is true.

`/fx'

Execute the instruction if flag f0 is false.

`/xt'

Execute the instruction if flag f1 is true.

`/xf'

Execute the instruction if flag f1 is false.

`/tt'

Execute the instruction if both flags f0 and f1 are true.

`/tf'

Execute the instruction if flag f0 is true and flag f1 is false.

9.9.2.5 Register Names

The D30V also has predefined symbols for these control registers and status bits:

psw

Processor Status Word

bpsw

Backup Processor Status Word

pc

Program Counter

bpc

Backup Program Counter

rpt_c

Repeat Count

rpt_s

Repeat Start address

rpt_e

Repeat End address

mod_s

Modulo Start address

mod_e

Modulo End address

iba

Instruction Break Address

f0

Flag 0

f1

Flag 1

f2

Flag 2

f3

Flag 3

f4

Flag 4

f5

Flag 5

f6

Flag 6

f7

Flag 7

s

Same as flag 4 (saturation flag)

v

Same as flag 5 (overflow flag)

va

Same as flag 6 (sticky overflow flag)

c

Same as flag 7 (carry/borrow flag)

b

Same as flag 7 (carry/borrow flag)

9.9.2.6 Addressing Modes

Rn

Register direct

@Rn

Register indirect

@Rn+

Register indirect with post-increment

@Rn-

Register indirect with post-decrement

@-SP

Register indirect with pre-decrement

@(disp, Rn)

Register indirect with displacement

addr

PC relative address (for branch or rep).

#imm

Immediate data (the `#' is optional and ignored)

9.9.3 Floating Point

9.9.4 Opcodes

9.10 H8/300 Dependent Features

9.10.1 Options
9.10.2 Syntax
9.10.3 Floating Point
9.10.4 H8/300 Machine Directives
9.10.5 Opcodes

9.10.1 Options

The Renesas H8/300 version of as has one machine-dependent option:

-h-tick-hex

Support H'00 style hex constants in addition to 0x00 style.

9.10.2 Syntax

9.10.2.1 Special Characters
9.10.2.2 Register Names
9.10.2.3 Addressing Modes

9.10.2.1 Special Characters

`;' is the line comment character.

`$' can be used instead of a newline to separate statements. Therefore you may not use `$' in symbol names on the H8/300.

9.10.2.2 Register Names

You can use predefined symbols of the form `rnh' and `rnl' to refer to the H8/300 registers as sixteen 8-bit general-purpose registers. n is a digit from `0' to `7'); for instance, both `r0h' and `r7l' are valid register names.

You can also use the eight predefined symbols `rn' to refer to the H8/300 registers as 16-bit registers (you must use this form for addressing).

On the H8/300H, you can also use the eight predefined symbols `ern' (`er0' ... `er7') to refer to the 32-bit general purpose registers.

The two control registers are called pc (program counter; a 16-bit register, except on the H8/300H where it is 24 bits) and ccr (condition code register; an 8-bit register). r7 is used as the stack pointer, and can also be called sp.

9.10.2.3 Addressing Modes

as understands the following addressing modes for the H8/300:

rn

Register direct

@rn

Register indirect

@(d, rn)

@(d:16, rn)

@(d:24, rn)

Register indirect: 16-bit or 24-bit displacement d from register n. (24-bit displacements are only meaningful on the H8/300H.)

@rn+

Register indirect with post-increment

@-rn

Register indirect with pre-decrement

@aa

@aa:8

@aa:16

@aa:24

Absolute address aa. (The address size `:24' only makes sense on the H8/300H.)

#xx

#xx:8

#xx:16

#xx:32

Immediate data xx. You may specify the `:8', `:16', or `:32' for clarity, if you wish; but as neither requires this nor uses it--the data size required is taken from context.

@@aa

@@aa:8

Memory indirect. You may specify the `:8' for clarity, if you wish; but as neither requires this nor uses it.

9.10.3 Floating Point

The H8/300 family has no hardware floating point, but the .float directive generates IEEE floating-point numbers for compatibility with other development tools.

9.10.4 H8/300 Machine Directives

as has the following machine-dependent directives for the H8/300:

.h8300h

Recognize and emit additional instructions for the H8/300H variant, and also make .int emit 32-bit numbers rather than the usual (16-bit) for the H8/300 family.

.h8300s

Recognize and emit additional instructions for the H8S variant, and also make .int emit 32-bit numbers rather than the usual (16-bit) for the H8/300 family.

.h8300hn

Recognize and emit additional instructions for the H8/300H variant in normal mode, and also make .int emit 32-bit numbers rather than the usual (16-bit) for the H8/300 family.

.h8300sn

Recognize and emit additional instructions for the H8S variant in normal mode, and also make .int emit 32-bit numbers rather than the usual (16-bit) for the H8/300 family.

On the H8/300 family (including the H8/300H) `.word' directives generate 16-bit numbers.

9.10.5 Opcodes

For detailed information on the H8/300 machine instruction set, see H8/300 Series Programming Manual. For information specific to the H8/300H, see H8/300H Series Programming Manual (Renesas).

as implements all the standard H8/300 opcodes. No additional pseudo-instructions are needed on this family.

The following table summarizes the H8/300 opcodes, and their arguments. Entries marked `*' are opcodes used only on the H8/300H.

Legend: Rs source register Rd destination register abs absolute address imm immediate data disp:N N-bit displacement from a register pcrel:N N-bit displacement relative to program counter add.b #imm,rd * andc #imm,ccr add.b rs,rd band #imm,rd add.w rs,rd band #imm,@rd * add.w #imm,rd band #imm,@abs:8 * add.l rs,rd bra pcrel:8 * add.l #imm,rd * bra pcrel:16 adds #imm,rd bt pcrel:8 addx #imm,rd * bt pcrel:16 addx rs,rd brn pcrel:8 and.b #imm,rd * brn pcrel:16 and.b rs,rd bf pcrel:8 * and.w rs,rd * bf pcrel:16 * and.w #imm,rd bhi pcrel:8 * and.l #imm,rd * bhi pcrel:16 * and.l rs,rd bls pcrel:8 * bls pcrel:16 bld #imm,rd bcc pcrel:8 bld #imm,@rd * bcc pcrel:16 bld #imm,@abs:8 bhs pcrel:8 bnot #imm,rd * bhs pcrel:16 bnot #imm,@rd bcs pcrel:8 bnot #imm,@abs:8 * bcs pcrel:16 bnot rs,rd blo pcrel:8 bnot rs,@rd * blo pcrel:16 bnot rs,@abs:8 bne pcrel:8 bor #imm,rd * bne pcrel:16 bor #imm,@rd beq pcrel:8 bor #imm,@abs:8 * beq pcrel:16 bset #imm,rd bvc pcrel:8 bset #imm,@rd * bvc pcrel:16 bset #imm,@abs:8 bvs pcrel:8 bset rs,rd * bvs pcrel:16 bset rs,@rd bpl pcrel:8 bset rs,@abs:8 * bpl pcrel:16 bsr pcrel:8 bmi pcrel:8 bsr pcrel:16 * bmi pcrel:16 bst #imm,rd bge pcrel:8 bst #imm,@rd * bge pcrel:16 bst #imm,@abs:8 blt pcrel:8 btst #imm,rd * blt pcrel:16 btst #imm,@rd bgt pcrel:8 btst #imm,@abs:8 * bgt pcrel:16 btst rs,rd ble pcrel:8 btst rs,@rd * ble pcrel:16 btst rs,@abs:8 bclr #imm,rd bxor #imm,rd bclr #imm,@rd bxor #imm,@rd bclr #imm,@abs:8 bxor #imm,@abs:8 bclr rs,rd cmp.b #imm,rd bclr rs,@rd cmp.b rs,rd bclr rs,@abs:8 cmp.w rs,rd biand #imm,rd cmp.w rs,rd biand #imm,@rd * cmp.w #imm,rd biand #imm,@abs:8 * cmp.l #imm,rd bild #imm,rd * cmp.l rs,rd bild #imm,@rd daa rs bild #imm,@abs:8 das rs bior #imm,rd dec.b rs bior #imm,@rd * dec.w #imm,rd bior #imm,@abs:8 * dec.l #imm,rd bist #imm,rd divxu.b rs,rd bist #imm,@rd * divxu.w rs,rd bist #imm,@abs:8 * divxs.b rs,rd bixor #imm,rd * divxs.w rs,rd bixor #imm,@rd eepmov bixor #imm,@abs:8 * eepmovw * exts.w rd mov.w rs,@abs:16 * exts.l rd * mov.l #imm,rd * extu.w rd * mov.l rs,rd * extu.l rd * mov.l @rs,rd inc rs * mov.l @(disp:16,rs),rd * inc.w #imm,rd * mov.l @(disp:24,rs),rd * inc.l #imm,rd * mov.l @rs+,rd jmp @rs * mov.l @abs:16,rd jmp abs * mov.l @abs:24,rd jmp @@abs:8 * mov.l rs,@rd jsr @rs * mov.l rs,@(disp:16,rd) jsr abs * mov.l rs,@(disp:24,rd) jsr @@abs:8 * mov.l rs,@-rd ldc #imm,ccr * mov.l rs,@abs:16 ldc rs,ccr * mov.l rs,@abs:24 * ldc @abs:16,ccr movfpe @abs:16,rd * ldc @abs:24,ccr movtpe rs,@abs:16 * ldc @(disp:16,rs),ccr mulxu.b rs,rd * ldc @(disp:24,rs),ccr * mulxu.w rs,rd * ldc @rs+,ccr * mulxs.b rs,rd * ldc @rs,ccr * mulxs.w rs,rd * mov.b @(disp:24,rs),rd neg.b rs * mov.b rs,@(disp:24,rd) * neg.w rs mov.b @abs:16,rd * neg.l rs mov.b rs,rd nop mov.b @abs:8,rd not.b rs mov.b rs,@abs:8 * not.w rs mov.b rs,rd * not.l rs mov.b #imm,rd or.b #imm,rd mov.b @rs,rd or.b rs,rd mov.b @(disp:16,rs),rd * or.w #imm,rd mov.b @rs+,rd * or.w rs,rd mov.b @abs:8,rd * or.l #imm,rd mov.b rs,@rd * or.l rs,rd mov.b rs,@(disp:16,rd) orc #imm,ccr mov.b rs,@-rd pop.w rs mov.b rs,@abs:8 * pop.l rs mov.w rs,@rd push.w rs * mov.w @(disp:24,rs),rd * push.l rs * mov.w rs,@(disp:24,rd) rotl.b rs * mov.w @abs:24,rd * rotl.w rs * mov.w rs,@abs:24 * rotl.l rs mov.w rs,rd rotr.b rs mov.w #imm,rd * rotr.w rs mov.w @rs,rd * rotr.l rs mov.w @(disp:16,rs),rd rotxl.b rs mov.w @rs+,rd * rotxl.w rs mov.w @abs:16,rd * rotxl.l rs mov.w rs,@(disp:16,rd) rotxr.b rs mov.w rs,@-rd * rotxr.w rs * rotxr.l rs * stc ccr,@(disp:24,rd) bpt * stc ccr,@-rd rte * stc ccr,@abs:16 rts * stc ccr,@abs:24 shal.b rs sub.b rs,rd * shal.w rs sub.w rs,rd * shal.l rs * sub.w #imm,rd shar.b rs * sub.l rs,rd * shar.w rs * sub.l #imm,rd * shar.l rs subs #imm,rd shll.b rs subx #imm,rd * shll.w rs subx rs,rd * shll.l rs * trapa #imm shlr.b rs xor #imm,rd * shlr.w rs xor rs,rd * shlr.l rs * xor.w #imm,rd sleep * xor.w rs,rd stc ccr,rd * xor.l #imm,rd * stc ccr,@rs * xor.l rs,rd * stc ccr,@(disp:16,rd) xorc #imm,ccr

Four H8/300 instructions (add, cmp, mov, sub) are defined with variants using the suffixes `.b', `.w', and `.l' to specify the size of a memory operand. as supports these suffixes, but does not require them; since one of the operands is always a register, as can deduce the correct size.

For example, since r0 refers to a 16-bit register,

mov r0,@foo is equivalent to mov.w r0,@foo

If you use the size suffixes, as issues a warning when the suffix and the register size do not match.

9.11 HPPA Dependent Features

9.11.1 Notes
9.11.2 Options
9.11.3 Syntax
9.11.4 Floating Point
9.11.5 HPPA Assembler Directives		HPPA Machine Directives
9.11.6 Opcodes

9.11.1 Notes

The format of the debugging sections has changed since the original as port (version 1.3X) was released; therefore, you must rebuild all HPPA objects and libraries with the new assembler so that you can debug the final executable.

The HPPA as port generates a small subset of the relocations available in the SOM and ELF object file formats. Additional relocation support will be added as it becomes necessary.

9.11.2 Options

9.11.3 Syntax

First, a colon may immediately follow a label definition. This is simply for compatibility with how most assembly language programmers write code.

Some obscure expression parsing problems may affect hand written code which uses the spop instructions, or code which makes significant use of the ! line separator.

as is much less forgiving about missing arguments and other similar oversights than the HP assembler. as notifies you of missing arguments as syntax errors; this is regarded as a feature, not a bug.

Finally, as allows you to use an external symbol without explicitly importing the symbol. Warning: in the future this will be an error for HPPA targets.

Special characters for HPPA targets include:

`;' is the line comment character.

`!' can be used instead of a newline to separate statements.

Since `$' has no special meaning, you may use it in symbol names.

9.11.4 Floating Point

9.11.5 HPPA Assembler Directives

as for the HPPA supports many additional directives for compatibility with the native assembler. This section describes them only briefly. For detailed information on HPPA-specific assembler directives, see HP9000 Series 800 Assembly Language Reference Manual (HP 92432-90001).

as does not support the following assembler directives described in the HP manual:

.endm .liston .enter .locct .leave .macro .listoff

Beyond those implemented for compatibility, as supports one additional assembler directive for the HPPA: .param. It conveys register argument locations for static functions. Its syntax closely follows the .export directive.

These are the additional directives in as for the HPPA:

.block n

.blockz n

Reserve n bytes of storage, and initialize them to zero.

.call

Mark the beginning of a procedure call. Only the special case with no arguments is allowed.

.callinfo [ param=value, ... ] [ flag, ... ]

Specify a number of parameters and flags that define the environment for a procedure.

param may be any of `frame' (frame size), `entry_gr' (end of general register range), `entry_fr' (end of float register range), `entry_sr' (end of space register range).

The values for flag are `calls' or `caller' (proc has subroutines), `no_calls' (proc does not call subroutines), `save_rp' (preserve return pointer), `save_sp' (proc preserves stack pointer), `no_unwind' (do not unwind this proc), `hpux_int' (proc is interrupt routine).

.code

Assemble into the standard section called `$TEXT$', subsection `$CODE$'.

.copyright "string"

In the SOM object format, insert string into the object code, marked as a copyright string.

.copyright "string"

In the ELF object format, insert string into the object code, marked as a version string.

.enter

Not yet supported; the assembler rejects programs containing this directive.

.entry

Mark the beginning of a procedure.

.exit

Mark the end of a procedure.

.export name [ ,typ ] [ ,param=r ]

Make a procedure name available to callers. typ, if present, must be one of `absolute', `code' (ELF only, not SOM), `data', `entry', `data', `entry', `millicode', `plabel', `pri_prog', or `sec_prog'.

param, if present, provides either relocation information for the procedure arguments and result, or a privilege level. param may be `argwn' (where n ranges from 0 to 3, and indicates one of four one-word arguments); `rtnval' (the procedure's result); or `priv_lev' (privilege level). For arguments or the result, r specifies how to relocate, and must be one of `no' (not relocatable), `gr' (argument is in general register), `fr' (in floating point register), or `fu' (upper half of float register). For `priv_lev', r is an integer.

.half n

Define a two-byte integer constant n; synonym for the portable as directive .short.

.import name [ ,typ ]

Converse of .export; make a procedure available to call. The arguments use the same conventions as the first two arguments for .export.

.label name

Define name as a label for the current assembly location.

.leave

Not yet supported; the assembler rejects programs containing this directive.

.origin lc

Advance location counter to lc. Synonym for the as portable directive .org.

.param name [ ,typ ] [ ,param=r ]

Similar to .export, but used for static procedures.

.proc

Use preceding the first statement of a procedure.

.procend

Use following the last statement of a procedure.

label .reg expr

Synonym for .equ; define label with the absolute expression expr as its value.

.space secname [ ,params ]

Switch to section secname, creating a new section by that name if necessary. You may only use params when creating a new section, not when switching to an existing one. secname may identify a section by number rather than by name.

If specified, the list params declares attributes of the section, identified by keywords. The keywords recognized are `spnum=exp' (identify this section by the number exp, an absolute expression), `sort=exp' (order sections according to this sort key when linking; exp is an absolute expression), `unloadable' (section contains no loadable data), `notdefined' (this section defined elsewhere), and `private' (data in this section not available to other programs).

.spnum secnam

Allocate four bytes of storage, and initialize them with the section number of the section named secnam. (You can define the section number with the HPPA .space directive.)

.string "str"

Copy the characters in the string str to the object file. See section Strings, for information on escape sequences you can use in as strings.

Warning! The HPPA version of .string differs from the usual as definition: it does not write a zero byte after copying str.

.stringz "str"

Like .string, but appends a zero byte after copying str to object file.

.subspa name [ ,params ]

.nsubspa name [ ,params ]

Similar to .space, but selects a subsection name within the current section. You may only specify params when you create a subsection (in the first instance of .subspa for this name).

If specified, the list params declares attributes of the subsection, identified by keywords. The keywords recognized are `quad=expr' ("quadrant" for this subsection), `align=expr' (alignment for beginning of this subsection; a power of two), `access=expr' (value for "access rights" field), `sort=expr' (sorting order for this subspace in link), `code_only' (subsection contains only code), `unloadable' (subsection cannot be loaded into memory), `comdat' (subsection is comdat), `common' (subsection is common block), `dup_comm' (subsection may have duplicate names), or `zero' (subsection is all zeros, do not write in object file).

.nsubspa always creates a new subspace with the given name, even if one with the same name already exists.

`comdat', `common' and `dup_comm' can be used to implement various flavors of one-only support when using the SOM linker. The SOM linker only supports specific combinations of these flags. The details are not documented. A brief description is provided here.

`comdat' provides a form of linkonce support. It is useful for both code and data subspaces. A `comdat' subspace has a key symbol marked by the `is_comdat' flag or `ST_COMDAT'. Only the first subspace for any given key is selected. The key symbol becomes universal in shared links. This is similar to the behavior of `secondary_def' symbols.

`common' provides Fortran named common support. It is only useful for data subspaces. Symbols with the flag `is_common' retain this flag in shared links. Referencing a `is_common' symbol in a shared library from outside the library doesn't work. Thus, `is_common' symbols must be output whenever they are needed.

`common' and `dup_comm' together provide Cobol common support. The subspaces in this case must all be the same length. Otherwise, this support is similar to the Fortran common support.

`dup_comm' by itself provides a type of one-only support for code. Only the first `dup_comm' subspace is selected. There is a rather complex algorithm to compare subspaces. Code symbols marked with the `dup_common' flag are hidden. This support was intended for "C++ duplicate inlines".

A simplified technique is used to mark the flags of symbols based on the flags of their subspace. A symbol with the scope SS_UNIVERSAL and type ST_ENTRY, ST_CODE or ST_DATA is marked with the corresponding settings of `comdat', `common' and `dup_comm' from the subspace, respectively. This avoids having to introduce additional directives to mark these symbols. The HP assembler sets `is_common' from `common'. However, it doesn't set the `dup_common' from `dup_comm'. It doesn't have `comdat' support.

.version "str"

Write str as version identifier in object code.

9.11.6 Opcodes

9.12 ESA/390 Dependent Features

9.12.1 Notes
9.12.2 Options
9.12.3 Syntax
9.12.4 Floating Point
9.12.5 ESA/390 Assembler Directives		ESA/390 Machine Directives
9.12.6 Opcodes

9.12.1 Notes

When used with the GNU CC compiler, the ESA/390 as will produce correct, fully relocated, functional binaries, and has been used to compile and execute large projects. However, many aspects should still be considered experimental; these include shared library support, dynamically loadable objects, and any relocation other than the 31-bit relocation.

9.12.2 Options

9.12.3 Syntax

A leading dot in front of directives is optional, and the case of directives is ignored; thus for example, .using and USING have the same effect.

A colon may immediately follow a label definition. This is simply for compatibility with how most assembly language programmers write code.

`#' is the line comment character.

`;' can be used instead of a newline to separate statements.

Since `$' has no special meaning, you may use it in symbol names.

Registers can be given the symbolic names r0..r15, fp0, fp2, fp4, fp6. By using thesse symbolic names, as can detect simple syntax errors. The name rarg or r.arg is a synonym for r11, rtca or r.tca for r12, sp, r.sp, dsa r.dsa for r13, lr or r.lr for r14, rbase or r.base for r3 and rpgt or r.pgt for r4.

`*' is the current location counter. Unlike `.' it is always relative to the last USING directive. Note that this means that expressions cannot use multiplication, as any occurrence of `*' will be interpreted as a location counter.

All labels are relative to the last USING. Thus, branches to a label always imply the use of base+displacement.

Many of the usual forms of address constants / address literals are supported. Thus,

.using *,r3 L r15,=A(some_routine) LM r6,r7,=V(some_longlong_extern) A r1,=F'12' AH r0,=H'42' ME r6,=E'3.1416' MD r6,=D'3.14159265358979' O r6,=XL4'cacad0d0' .ltorg

should all behave as expected: that is, an entry in the literal pool will be created (or reused if it already exists), and the instruction operands will be the displacement into the literal pool using the current base register (as last declared with the .using directive).

9.12.4 Floating Point

9.12.5 ESA/390 Assembler Directives

as for the ESA/390 supports all of the standard ELF/SVR4 assembler directives that are documented in the main part of this documentation. Several additional directives are supported in order to implement the ESA/390 addressing model. The most important of these are .using and .ltorg

These are the additional directives in as for the ESA/390:

.dc

A small subset of the usual DC directive is supported.

.drop regno

Stop using regno as the base register. The regno must have been previously declared with a .using directive in the same section as the current section.

.ebcdic string

Emit the EBCDIC equivalent of the indicated string. The emitted string will be null terminated. Note that the directives .string etc. emit ascii strings by default.

EQU

The standard HLASM-style EQU directive is not supported; however, the standard as directive .equ can be used to the same effect.

.ltorg

Dump the literal pool accumulated so far; begin a new literal pool. The literal pool will be written in the current section; in order to generate correct assembly, a .using must have been previously specified in the same section.

.using expr,regno

Use regno as the base register for all subsequent RX, RS, and SS form instructions. The expr will be evaluated to obtain the base address; usually, expr will merely be `*'.

This assembler allows two .using directives to be simultaneously outstanding, one in the .text section, and one in another section (typically, the .data section). This feature allows dynamically loaded objects to be implemented in a relatively straightforward way. A .using directive must always be specified in the .text section; this will specify the base register that will be used for branches in the .text section. A second .using may be specified in another section; this will specify the base register that is used for non-label address literals. When a second .using is specified, then the subsequent .ltorg must be put in the same section; otherwise an error will result.

Thus, for example, the following code uses r3 to address branch targets and r4 to address the literal pool, which has been written to the .data section. The is, the constants =A(some_routine), =H'42' and =E'3.1416' will all appear in the .data section.

.data .using LITPOOL,r4 .text BASR r3,0 .using *,r3 B START .long LITPOOL START: L r4,4(,r3) L r15,=A(some_routine) LTR r15,r15 BNE LABEL AH r0,=H'42' LABEL: ME r6,=E'3.1416' .data LITPOOL: .ltorg

Note that this dual-.using directive semantics extends and is not compatible with HLASM semantics. Note that this assembler directive does not support the full range of HLASM semantics.

9.12.6 Opcodes

9.13 80386 Dependent Features

The i386 version as supports both the original Intel 386 architecture in both 16 and 32-bit mode as well as AMD x86-64 architecture extending the Intel architecture to 64-bits.

9.13.1 Options
9.13.2 x86 specific Directives		X86 specific directives
9.13.3 AT&T Syntax versus Intel Syntax
9.13.4 Instruction Naming
9.13.6 Register Naming
9.13.7 Instruction Prefixes
9.13.8 Memory References
9.13.9 Handling of Jump Instructions
9.13.10 Floating Point
9.13.11 Intel's MMX and AMD's 3DNow! SIMD Operations
9.13.12 Writing 16-bit Code
9.13.14 Specifying CPU Architecture		Specifying an x86 CPU architecture
9.13.13 AT&T Syntax bugs
9.13.15 Notes

9.13.1 Options

The i386 version of as has a few machine dependent options:

--32 | --64

Select the word size, either 32 bits or 64 bits. Selecting 32-bit implies Intel i386 architecture, while 64-bit implies AMD x86-64 architecture.

These options are only available with the ELF object file format, and require that the necessary BFD support has been included (on a 32-bit platform you have to add --enable-64-bit-bfd to configure enable 64-bit usage and use x86-64 as target platform).

-n

By default, x86 GAS replaces multiple nop instructions used for alignment within code sections with multi-byte nop instructions such as leal 0(%esi,1),%esi. This switch disables the optimization.

--divide

On SVR4-derived platforms, the character `/' is treated as a comment character, which means that it cannot be used in expressions. The `--divide' option turns `/' into a normal character. This does not disable `/' at the beginning of a line starting a comment, or affect using `#' for starting a comment.

-march=CPU[+EXTENSION...]

This option specifies the target processor. The assembler will issue an error message if an attempt is made to assemble an instruction which will not execute on the target processor. The following processor names are recognized: i8086, i186, i286, i386, i486, i586, i686, pentium, pentiumpro, pentiumii, pentiumiii, pentium4, prescott, nocona, core, core2, corei7, l1om, k6, k6_2, athlon, opteron, k8, amdfam10, generic32 and generic64.

In addition to the basic instruction set, the assembler can be told to accept various extension mnemonics. For example, -march=i686+sse4+vmx extends i686 with sse4 and vmx. The following extensions are currently supported: 8087, 287, 387, no87, mmx, nommx, sse, sse2, sse3, ssse3, sse4.1, sse4.2, sse4, nosse, avx, noavx, vmx, smx, xsave, aes, pclmul, fma, movbe, ept, clflush, syscall, rdtscp, 3dnow, 3dnowa, sse4a, sse5, svme, abm and padlock. Note that rather than extending a basic instruction set, the extension mnemonics starting with no revoke the respective functionality.

When the .arch directive is used with `-march', the .arch directive will take precedent.

-mtune=CPU

This option specifies a processor to optimize for. When used in conjunction with the `-march' option, only instructions of the processor specified by the `-march' option will be generated.

Valid CPU values are identical to the processor list of `-march=CPU'.

-msse2avx

This option specifies that the assembler should encode SSE instructions with VEX prefix.

-msse-check=none

-msse-check=warning

-msse-check=error

These options control if the assembler should check SSE intructions. `-msse-check=none' will make the assembler not to check SSE instructions, which is the default. `-msse-check=warning' will make the assembler issue a warning for any SSE intruction. `-msse-check=error' will make the assembler issue an error for any SSE intruction.

-mmnemonic=att

-mmnemonic=intel

This option specifies instruction mnemonic for matching instructions. The .att_mnemonic and .intel_mnemonic directives will take precedent.

-msyntax=att

-msyntax=intel

This option specifies instruction syntax when processing instructions. The .att_syntax and .intel_syntax directives will take precedent.

-mnaked-reg

This opetion specifies that registers don't require a `%' prefix. The .att_syntax and .intel_syntax directives will take precedent.

9.13.2 x86 specific Directives

.lcomm symbol , length[, alignment]

Reserve length (an absolute expression) bytes for a local common denoted by symbol. The section and value of symbol are those of the new local common. The addresses are allocated in the bss section, so that at run-time the bytes start off zeroed. Since symbol is not declared global, it is normally not visible to ld. The optional third parameter, alignment, specifies the desired alignment of the symbol in the bss section.

This directive is only available for COFF based x86 targets.

9.13.3 AT&T Syntax versus Intel Syntax

as now supports assembly using Intel assembler syntax. .intel_syntax selects Intel mode, and .att_syntax switches back to the usual AT&T mode for compatibility with the output of gcc. Either of these directives may have an optional argument, prefix, or noprefix specifying whether registers require a `%' prefix. AT&T System V/386 assembler syntax is quite different from Intel syntax. We mention these differences because almost all 80386 documents use Intel syntax. Notable differences between the two syntaxes are:

• AT&T immediate operands are preceded by `$'; Intel immediate operands are undelimited (Intel `push 4' is AT&T `pushl $4'). AT&T register operands are preceded by `%'; Intel register operands are undelimited. AT&T absolute (as opposed to PC relative) jump/call operands are prefixed by `*'; they are undelimited in Intel syntax.

• AT&T and Intel syntax use the opposite order for source and destination operands. Intel `add eax, 4' is `addl $4, %eax'. The `source, dest' convention is maintained for compatibility with previous Unix assemblers. Note that `bound', `invlpga', and instructions with 2 immediate operands, such as the `enter' instruction, do not have reversed order. 9.13.13 AT&T Syntax bugs.

• In AT&T syntax the size of memory operands is determined from the last character of the instruction mnemonic. Mnemonic suffixes of `b', `w', `l' and `q' specify byte (8-bit), word (16-bit), long (32-bit) and quadruple word (64-bit) memory references. Intel syntax accomplishes this by prefixing memory operands (not the instruction mnemonics) with `byte ptr', `word ptr', `dword ptr' and `qword ptr'. Thus, Intel `mov al, byte ptr foo' is `movb foo, %al' in AT&T syntax.

• Immediate form long jumps and calls are `lcall/ljmp $section, $offset' in AT&T syntax; the Intel syntax is `call/jmp far section:offset'. Also, the far return instruction is `lret $stack-adjust' in AT&T syntax; Intel syntax is `ret far stack-adjust'.

• The AT&T assembler does not provide support for multiple section programs. Unix style systems expect all programs to be single sections.

9.13.4 Instruction Naming

Instruction mnemonics are suffixed with one character modifiers which specify the size of operands. The letters `b', `w', `l' and `q' specify byte, word, long and quadruple word operands. If no suffix is specified by an instruction then as tries to fill in the missing suffix based on the destination register operand (the last one by convention). Thus, `mov %ax, %bx' is equivalent to `movw %ax, %bx'; also, `mov $1, %bx' is equivalent to `movw $1, bx'. Note that this is incompatible with the AT&T Unix assembler which assumes that a missing mnemonic suffix implies long operand size. (This incompatibility does not affect compiler output since compilers always explicitly specify the mnemonic suffix.)

Almost all instructions have the same names in AT&T and Intel format. There are a few exceptions. The sign extend and zero extend instructions need two sizes to specify them. They need a size to sign/zero extend from and a size to zero extend to. This is accomplished by using two instruction mnemonic suffixes in AT&T syntax. Base names for sign extend and zero extend are `movs...' and `movz...' in AT&T syntax (`movsx' and `movzx' in Intel syntax). The instruction mnemonic suffixes are tacked on to this base name, the from suffix before the to suffix. Thus, `movsbl %al, %edx' is AT&T syntax for "move sign extend from %al to %edx." Possible suffixes, thus, are `bl' (from byte to long), `bw' (from byte to word), `wl' (from word to long), `bq' (from byte to quadruple word), `wq' (from word to quadruple word), and `lq' (from long to quadruple word).

Different encoding options can be specified via optional mnemonic suffix. `.s' suffix swaps 2 register operands in encoding when moving from one register to another.

The Intel-syntax conversion instructions

• `cbw' -- sign-extend byte in `%al' to word in `%ax',

• `cwde' -- sign-extend word in `%ax' to long in `%eax',

• `cwd' -- sign-extend word in `%ax' to long in `%dx:%ax',

• `cdq' -- sign-extend dword in `%eax' to quad in `%edx:%eax',

• `cdqe' -- sign-extend dword in `%eax' to quad in `%rax' (x86-64 only),

• `cqo' -- sign-extend quad in `%rax' to octuple in `%rdx:%rax' (x86-64 only),

are called `cbtw', `cwtl', `cwtd', `cltd', `cltq', and `cqto' in AT&T naming. as accepts either naming for these instructions.

Far call/jump instructions are `lcall' and `ljmp' in AT&T syntax, but are `call far' and `jump far' in Intel convention.

9.13.5 AT&T Mnemonic versus Intel Mnemonic

as supports assembly using Intel mnemonic. .intel_mnemonic selects Intel mnemonic with Intel syntax, and .att_mnemonic switches back to the usual AT&T mnemonic with AT&T syntax for compatibility with the output of gcc. Several x87 instructions, `fadd', `fdiv', `fdivp', `fdivr', `fdivrp', `fmul', `fsub', `fsubp', `fsubr' and `fsubrp', are implemented in AT&T System V/386 assembler with different mnemonics from those in Intel IA32 specification. gcc generates those instructions with AT&T mnemonic.